Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-01-25
2001-04-10
Crane, Sara (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S408000, C438S162000, C438S163000
Reexamination Certificate
active
06215153
ABSTRACT:
BACKGROUND OF THE, INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a metal oxide silicon field effect transistor (MOSFET) and a method for fabricating the same.
2. Background of the Related Art
The reduction of the size of semiconductor devices results in high integration, especially the size of the transistors. Such a reduction reduces the channel lengths, which causes punch-through and increases leakage current between a source and a drain due to a shortened distance between the source and drain.
FIGS. 1A-1D
illustrate processes for fabricating a MOSFET. Referring to
FIG. 1A
, after implanting channel ions into a surface of a first conductive type semiconductor substrate
11
, an insulating film is formed on an entire surface of the semiconductor substrate
11
and then patterned to form a gate insulating film
12
on a channel region
17
of the semiconductor substrate
11
. A polysilicon layer
13
for a gate electrode is formed on the gate insulating film
12
. As shown in
FIG. 1B
, a photoresist (not shown) is coated on the polysilicon layer
13
. The photoresist is subjected to an exposure process and a development process for patterning the photoresist to define a gate electrode region. The polysilicon layer
13
is selectively dry-etched using the patterned photoresist as a mask for dry-etching, thereby forming a gate electrode
13
a.
Impurity ions are implanted into the semiconductor substrate
11
using the gate electrode
13
a
as a mask for ion-implantation, thereby forming LDD (Lightly Doped Drain) regions
14
in the surface of the semiconductor substrate
11
at both sides of the gate electrode
13
a
. Ions having the first conductivity, same as the channel are implanted vertically or tiltly, to form first conductive impurity regions
14
a
. The impurity regions
14
a
improve short channel characteristic.
As shown in
FIG. 1C
, an insulating film is formed on the entire surface of the substrate
11
including the gate electrode
13
a
and then etched-back to form insulating sidewalls
15
at both sides of the gate electrode
13
a
. When impurities ions are heavily implanted into the semiconductor substrate
11
using the insulating sidewalls
15
and the gate electrode
13
a
as masks for ion-implantation, impurity regions
16
are formed as a sources and a drain D, as shown in FIG.
1
D.
However, the process for fabricating a MOSFET according to the background art has the following problem. When the impurity ions are implanted to form the halo regions for improving short channel characteristic, the impurity ions are implanted heavier at the edge portions than a center portion of the channel, thereby resulting in an increase of a threshold voltage and also changing the characteristic of a threshold voltage according to a length of the channel at the end.
SUMMARY OF THE INVENTION
An object of the present invention is to substantially obviate one or more of the problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide an MOSFET and a method of fabricating the same which can prevent variation of a threshold voltage due to halo ions, thereby improving electrical characteristics of the MOSFET.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, the MOSFET includes a first conductive type substrate, having a channel therein, a gate electrode formed on the channel region, a high concentration impurity regions of a second conductive type formed on the surface of the substrate and adjacent to both sides of the channel region, low concentration impurity regions of a second conductive type formed between the channel region and high concentration impurity regions, impurity regions of the first conductivity type formed beneath the low concentration impurity regions of the second conductive type and diffusion barriers formed between the low concentration impurity regions of the second conductive type and the impurity regions of the first conductive type.
Another aspect of the present invention includes a method for fabricating an MOSFET including the steps of forming two diffusion barrier layers spaced from each other on an substrate of the first conductive type, growing an epitaxial layer on the entire surface of the substrate with a thickness enough to cover the barrier layers, forming a gate insulating film on a region of epitaxial layer and forming a gate electrode on the gate insulating film, implanting impurity-ions of a second conductive type having a low concentration into the epitaxial layer to form low concentration impurity regions of the second conductive type, implanting impurity-ions of the first conductive type into the substrate to form impurity regions of the first conductive type and implanting impurity-ions the second conductive type having a high concentration into the epitaxial layer including the substrate to form high concentration impurity regions in the surface of the epitaxial layer and at both sides of the gate electrode.
The present invention can be achieved in a whole or in parts by a semiconductor device, comprising: a substrate; a control electrode insulatively formed over the substrate; first and second impurity regions of a first conductivity type formed in the substrate and substantially adjacent to first and second sides, respectively, of the control electrode, each of the first and second impurity regions having first and second concentration regions; a third impurity region of a second conductivity type formed beneath the first concentration region of the first and second impurity regions; and an insulation layer formed between the third impurity region and the first concentration region of the first and second impurity regions.
The present invention can be also achieved in a whole or in parts by a method of making a semiconductor device, the method comprising the steps of: forming two insulation layers spaced from each other on a semiconductor substrate; forming a semiconductor layer on the entire surface of the semiconductor substrate with a thickness enough to cover the two insulation layers; forming a gate insulating film on a region of the semiconductor layer and forming a gate electrode on the gate insulating film; forming first impurity regions in the semiconductor layer and substantially next to opposing sides of the gate electrode, each first impurity region including an impurity portion formed over a corresponding one of the two insulation layers; forming second impurity regions beneath the two insulation layers.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objects and advantages of the invention may be realized and attained as particularly pointed out in the appended claims.
REFERENCES:
patent: 4700454 (1987-10-01), Baerg et al.
patent: 4810664 (1989-03-01), Kamins et al.
patent: 4837186 (1989-06-01), Ohata et al.
patent: 4908681 (1990-03-01), Nishida et al.
patent: 5049992 (1991-09-01), Citta et al.
patent: 5262854 (1993-11-01), Ng
patent: 5565925 (1996-10-01), Kinouchi et al.
patent: 5593928 (1997-01-01), Lee
patent: 5614952 (1997-03-01), Boyce et al.
patent: 5641980 (1997-06-01), Yamaguchi et al.
patent: 5712173 (1998-01-01), Liu et al.
patent: 5977602 (1999-11-01), Gardner et al.
Crane Sara
Fleshner & Kim LLP
Hyundai Electronics Industries Co,. Ltd.
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