MOS type semiconductor device having electrostatic discharge...

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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C257S173000, C257S174000, C257S356000, C257S357000, C257S358000, C257S359000, C257S360000, C257S363000, C257S368000

Reexamination Certificate

active

11111797

ABSTRACT:
In a semiconductor device having an electrostatic discharge protection arrangement, a semiconductor substrate exhibits a first conductivity type. First and second impurity regions each exhibiting a second conductivity type are formed in the semiconductor substrate. A channel region is formed in the semiconductor substrate between the first and second impurity regions. A first conductive area is defined on the first impurity region in the vicinity of the channel region. A second conductive area is defined on the first impurity region so as to be supplied with an electrostatic discharge current. A third conductive area is defined on the first impurity region to establish an electrical connection between the first and second conductive area. At least one heat-radiation area is defined in the third conductive area so as to be at least partially isolated therefrom and thermally contacted with the first conductive area.

REFERENCES:
patent: 6407445 (2002-06-01), Vashchenko et al.
patent: 6495888 (2002-12-01), Yamato
patent: 6559507 (2003-05-01), Vashchenko et al.
patent: 6664599 (2003-12-01), Chen et al.
patent: 6777784 (2004-08-01), Vashchenko et al.
patent: 2004/0155300 (2004-08-01), Baird et al.
patent: 2004/0173836 (2004-09-01), Oh et al.
patent: 2-271674 (1990-11-01), None
patent: 2773221 (1998-04-01), None
patent: 2996722 (1999-10-01), None
patent: 2000-156501 (2000-06-01), None
patent: WO 91/05371 (1991-04-01), None
Article by V.A. Vashchenko et al.; entitled “Increasing the ESD Protection Capability of Over-Voltage NMOS Structures by Comb-Ballasting Region Design”; Reliability Physics Symposium Proceedings; 2003; 41th Annual 2003 IEEE International; Mar. 30-Apr. 4, 2003; pp. 261-268.
Article by Bart Keppens et al.; entitled “Active-Area-Segmentation (AAS) Technique for Compact, ESD Robust, Fully Silicided NMOS Design”; Sep. 2003.
Japanese Patent Abstract of 5-505064, published Jul. 29, 1993.

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