MOS type semiconductor device having a low concentration impurit

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

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257336, 257344, 257408, H01L 2976, H01L 2994, H01L 31062, H01L 31113

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active

055127711

ABSTRACT:
An MOS type semiconductor device comprises a semiconductor substrate including a p-type region doped with p-type impurities and having a surface and an MOS transistor formed in the p-type region, the MOS transistor including: an n-type source region formed in the p-type region; an n-type drain region formed in the p-type region and separated from the n-type source region by a predetermined distance; a channel region formed in the p-type region and located between the n-type source and drain regions; a pair of n-type impurity diffusion regions formed on both sides of the channel region and having an impurity concentration lower than that of the n-type source region; a gate insulating film formed on the surface of the semiconductor substrate, the gate insulating film directly covering the channel region and the pair of n-type impurity diffusion regions; a gate electrode formed on the gate insulating film; and side walls formed on the sides of the gate electrode, wherein each of the side walls has a bottom portion extending along the surface of the semiconductor substrate from each side of the gate electrode, and each of the n-type source and drain regions has a first portion covered with the bottom portion of the side wall and a second portion not covered with the bottom portion, a thickness of the first portion being smaller than that of the second portion. A method for fabricating such an MOS type semiconductor device is also provided.

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Huang, T. Y. et al., "A Novel Submicron LDD Transistor With Inverse-T Gate Structure", IEEE IEDM, Technical Digest, pp. 742-745 (1986).
Izawa, R. et al, "Impact of the Gate-Drain Overlapped Device" (Gold).
"For Deep Submicrometer VLSI", IEEE Transactions on Electron Devices, vol. 35, No. 12, pp. 2088-2093 (Dec. 1988).
S. Hsia et al., "Polysilicon Oxidation Self-Aligned MOS (POSA MOS)-A New Self-Aligned Double Source/Drain Ion Implantation Technique for VLSI" IEEE Electron Device Letters, vol. EDL-3, No. 2, pp. 40-42 (FEb. 1982).
EPO, Partial European Search Report for counterpart application EP93 11 7804, mailed Dec. 28, 1993.

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