MOS type random access memory with interference noise eliminator

Details MOS type random access memory with interference noise eliminator MOS type random access memory with interference noise eliminator

1989-09-26

1991-10-29

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Differential sensing

365203, 365149, G11C 1134

Patent

active

050620797

ABSTRACT:
A MOS type random access memory disclosed has a plurality of pairs of sequentially aligned folded type bit lines each of which has a first bit line and a second bit line. Memory cells are arranged at points of intersection between a memory cell word line and the first bit lines. Dummy cells are arranged at points of intersection of a dummy cell word line and the second bit lines. Sense amplifier circuits are connected to the bit line pairs, respectively. In a data read mode of the memory, when a bit data is read from a certain memory cell which is connected to a first word line selected and a first bit line of a selected bit line pair, a second bit line onto which a data voltage is read from a dummy cell of the selected bit line pair is forcedly fixed to a precharge voltage produced by a precharge voltage generator in a presented time interval after the first word line is selected and before a certain sense amplifier circuit connected to the selected bit line pair gets activated, whereby interference noise may be eliminated which is introduced onto the selected bit line pair from a bit line pair adjacent to the selected bit line pair.

REFERENCES:
patent: 4379344 (1983-04-01), Ozawa et al.
patent: 4667311 (1987-05-01), Ulhaq

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