MOS transistors with improved gate dielectrics

Details MOS transistors with improved gate dielectrics MOS transistors with improved gate dielectrics

2000-03-07

2003-07-08

Pham, Long (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S221000, C257S287000, C257S296000, C257S355000, C257S359000, C257S404000

Reexamination Certificate

active

06590241

ABSTRACT:

FIELD OF THE INVENTION
The invention relates to improved gate dielectric structures for increasing the gate capacitance in MOS transistor devices.
BACKGROUND OF THE INVENTION
As the size shrinks and speed of silicon devices increases, current leakage and other reliability problems increase. In MOS devices, small device dimensions, high speed performance, and low operating voltages are primary issues facing the continued development of improved devices. With a given budget for operating voltages the main option for the device designer is a trade-off between low power and high speed. The operating voltage scales with device dimensions which are relatively fixed for the current generation of technology. Thus the most promising option left for device improvement is to increase the coupling ratio by increasing the gate capacitance.
The main options for increasing the gate capacitance are to reduce the gate dielectric thickness or to alter the dielectric properties of the gate dielectric material. Device and process designers to date have recognized that as the gate dielectric thickness shrinks, the potential for leakage and other electrical defects increases. Thus the quality of the dielectric material used is important. The highest quality material so far developed in silicon technology for low defects and for low surface state density is SiO
2
. An important advantage of SiO
2
is that it can be grown from the silicon substrate. It is well known that grown oxides tend to have fewer defects, e.g. pinholes, than deposited materials. Thus SiO
2
has persisted as the dielectric material of choice in most silicon device structures.
In spite of the popularity of SiO
2
as a dielectric material, efforts continue in a search for new dielectric materials. The use of Ta
2
O
5
as a dielectric has been proposed for MOSFETs (see Youichi Momiyama et al, “Ultra-Thin Ta
2
O
5
/SiO
2
Gate Insulator with TiN Gate Technology for 0.1 &mgr;m MOSFETs”, 1997 Symposium on VLSI Technology Digest of Technical Papers, pp. 135, 136. This material has also been proposed for stacked and trench capacitors in DRAM structures (see Tomonori Aoyama et al, “Leakage Current Mechanism of Amorphous and Polycrystalline Ta
2
O
5
Films Grown by Chemical Vapor Deposition”, J. Electrochem. Soc., Vol. 143, No. 3, pp. 977-983, March 1996. The formula Ta
2
O
5
represents the most common stoichiometric tantalum oxide, but this material, when deposited by most thin film deposition techniques, is often not stoichiometric. Therefore it is frequently referred to as TaO
x
which is the generic reference used in this description. The oxygen content x will typically be a value between 1.5 and 3.
While there is interest in Ta
2
O
5
as a gate material it has been found to be incompatible with conventional silicon device processing. The gate dielectric in e.g. silicon gate device fabrication is exposed to heating steps at temperatures of the order of 850° C. and above. These temperatures are required for annealing and drive in of the source/drain implant. The conventional gate dielectric material, SiO
2
, easily withstands these temperatures, and remains amorphous to temperatures as high as 1100° C. However, TaO
x
crystallizes at a temperature of approximately 650-700° C. In the crystal form, TaO
x
is not suitable for high performance device fabrication because of the formation of a substantial SiO
2
interfacial layer at the surface of the silicon substrate during high temperature processing. The excessively thick SiO
2
layer limits the objective of having a specific capacitance, C/A, material for the gate.
Crystallization of the Ta
2
O
5
can also lead to non-uniformities in the capacitance on a length scale due to variations in the density of grain boundaries and inhomogeneities from gate to gate leading to unacceptable variations in threshold voltage in a given integrated circuit.
A modified form of TaO
x
, Ta—Al—O, has been proposed for capacitor structures. See Nomura et al, U.S. Pat. No. 4,602,192. However, it has not been used in MOS transistor gate structures and there is no indication that it is compatible with the high temperature conditions required in the fabrication of these devices.
Use of Ta—Al—O has also been described in connection with thin film transistors. See Fujikawa et al, J. Appl. Phys, 75, 2538 (1994). These structures typically do not use single crystal silicon substrates and there is no indication of the electrical performance of a Ta—Al—O/silicon interface. Moreover, the devices were processed at temperatures well below those encountered in the process of this invention.
SUMMARY OF THE INVENTION
We have developed a new MOS gate structure, with improved dielectric properties, using Ta—Al—O or Ta—Si—O as the gate dielectric material. We have discovered that MOS transistor gates with these materials have exceptional electrical properties and these properties are not degraded by high temperature processing. Even after high temperature anneal, these materials have low leakage currents, show relatively little growth of interfacial SiO
2
, and thus have high specific capacitance with low interface state density. The dielectric properties of these MOS gates are substantially improved over conventional silicon gate structures and allow new options for MOS device designers. Use of these gate dielectric materials is fully compatible with state of the art silicon device processing, and they have low defect potential comparable to that of SiO
2
but with a substantially higher K.


REFERENCES:
patent: 5292673 (1994-03-01), Shinriki et al.
patent: 5977582 (1999-11-01), Fleming et al.
patent: 08-185978 (1996-07-01), None

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