MOS transistors with improved gate dielectrics

Details MOS transistors with improved gate dielectrics MOS transistors with improved gate dielectrics

1998-05-28

2000-05-09

Niebling, John F.

Semiconductor device manufacturing: process

Coating of substrate containing semiconductor region or of...

Insulative material deposited upon semiconductive substrate

438287, H01L 2131

Patent

active

060604069

ABSTRACT:
The specification describes silicon MOS devices with gate dielectrics having the composition Ta.sub.1-x Al.sub.x O.sub.y, where x is 0.03-0.7 and y is 1.5-3, Ta.sub.1-x Si.sub.x O.sub.y, where x is 0.05-0.15, and y is 1.5-3, and Ta.sub.1-x-z Al.sub.x Si.sub.z O.sub.y, where 0.7>x+z>0.05, z<0.15 and y is 1.5-3. By comparison with the standard SiO.sub.2 gate dielectric material, these materials provide improved dielectric properties and also remain essentially amorphous to high temperatures. This retards formation of SiO.sub.2 interfacial layers which otherwise dominate the gate dielectric properties and reduce the overall effectiveness of using a high dielectric material.

REFERENCES:
patent: 4789645 (1988-12-01), Calviello et al.
patent: 5552337 (1996-09-01), Kwon et al.
patent: 5677015 (1997-10-01), Hasegawa
patent: 5963810 (1999-10-01), Gardner et al.

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