MOS transistors having low-resistance salicide gates and a...

Details MOS transistors having low-resistance salicide gates and a... MOS transistors having low-resistance salicide gates and a...

2007-05-02

2009-06-02

Blum, David S (Department: 2813)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

Reexamination Certificate

active

07541271

ABSTRACT:
A method for forming a self-aligned contact between two MOS transistors is described. The method supports the use of low-resistivity silicides for the formation of contacts in nanometer applications that employ polycide techniques. Silicon nitride and photoresist material act as dual masks in the formation of the self-aligned contact.

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patent: 2004/0018679 (2004-01-01), Yu et al.
patent: 2004/0115874 (2004-06-01), Amon et al.
patent: 1440070 (2003-09-01), None

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