MOS transistor with improved radiation hardness

Details MOS transistor with improved radiation hardness MOS transistor with improved radiation hardness

1988-02-01

1990-11-27

James, Andrew J.

357 2311, 357 237, H01L 2978

Patent

active

049740512

ABSTRACT:
An MOS transistor is disclosed which has a guard ring for prevention of source-to-drain conduction through the isolation oxide after exposure to ionizing radiation. In the described example of an n-channel transistor, a p+ region is formed at the edges of the source region in a self-aligned fashion relative to the gate electrode so as not to extend under the gate to contact the drain region. This p+ region forms a diode which retards source-drain conduction even if a channel is formed under the isolating field oxide where the gate electrode overlaps onto the field oxide. The structure may be silicided for improved series resistance. An example of the transistor formed in an SOI configuration is also disclosed.

REFERENCES:
patent: 4053916 (1977-10-01), Cricchi et al.
patent: 4591890 (1986-05-01), Lund et al.
patent: 4753896 (1988-06-01), Matlousian
Lee et al., "Island Edge Effects in CMOS/SOS Transistors," IEEE Trans. E.D., vol. ED-25, No. 8 (Aug. 1978), pp. 971-978.
Tihanyi et al., " Properties of ESFI MOS Transistors Due to the Floating Substrate and the Finite Volume," IEEE TRans. E.D., vol. ED-22, No. 11 (Nov. 1975), pp. 1017-1023.
Tihanyi et al., "Influence of the Floating Substrate Potential on the Characteristics of ESFI MOS Transistors," Solid State Electronics, vol. 18 (Pergamon, 1975), pp. 309-314.

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