MOS transistor with a controlled threshold voltage

Details MOS transistor with a controlled threshold voltage MOS transistor with a controlled threshold voltage

2006-01-24

2006-01-24

Flynn, Nathan J. (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S257000, C257S347000, C257S348000, C257S035000

Reexamination Certificate

active

06989569

ABSTRACT:
A MOS transistor with a controlled threshold voltage includes a SOI which includes a substrate composed of a semi-conducting material, a single crystal layer composed of a semi-conducting material and an insulating layer interposed between the substrate and the single crystal layer. The single crystal layer is formed therein with a source region, a drain region and a surrounded region surrounded by the source region and the drain region. The surrounded region includes a depletion layer having a composition surface which is in contact with the insulating layer. The MOS transistor comprises an EIB-MOS transistor of which the substrate is adapted to be applied with a voltage of a first polarity for inducing charges of a second polarity over the composition surface of the surrounded region.

REFERENCES:
patent: 5698885 (1997-12-01), Warashina et al.
patent: 6100567 (2000-08-01), Burr
patent: 7-131025 (1995-05-01), None
patent: 9-162417 (1997-06-01), None
patent: 10-256556 (1998-09-01), None
patent: 2000260991 (2000-09-01), None
F. Assaderaghi et al, “A Dynamic Threshold Voltage MOSFET (DTMOS) for Ultra-Low Voltage Operation”, IEEE, 1994, 33.1.1-33.1.4.

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