MOS transistor having reduced source/drain extension sheet...

Details MOS transistor having reduced source/drain extension sheet... MOS transistor having reduced source/drain extension sheet...

2003-08-14

2004-11-09

Jackson, Jerome (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S335000, C257S336000

Reexamination Certificate

active

06815770

ABSTRACT:

BACKGROUND OF INVENTION
1. Field of the Invention
The present invention relates to a metal-oxide-semiconductor (MOS) transistor structure and, more particularly, to a MOS transistor structure having reduced sheet resistance in ultra-shallow source/drain extension regions and method of fabrication.
2. Description of the Prior Art
Continued device scaling demands that source/drain (S/D) junctions of MOS transistor devices become thinner and thinner to avoid short channel effect. However, the prior art MOS structure has a drawback in that the shallower the S/D extension is, the greater the sheet resistance occurs in operation. As known to those skilled in the art, large sheet resistance leads to insufficient saturation currents. The situation becomes worse when the MOS device is a
FIG. 1
is a schematic cross-sectional diagram showing a prior art PMOS transistor
10
having ultra-shallow junction S/D extensions
32
. The prior art PMOS transistor
10
includes a poly gate
12
formed on an N well
16
of a silicon substrate. A gate oxide layer
14
is formed between the gate
12
and the silicon substrate. Spacers
18
are disposed on opposite sidewalls of the gate
12
. A P
−
ultra-shallow junction S/D extension
32
is formed underneath the spacer
18
within the N well
16
. Next to the outer edge to the spacer
18
, a raised silicide layer
42
is provided on P
+
source/drain region
34
. A silicide layer
44
is formed on the top of the poly gate
12
. Typically, the spacer
18
consists of an offset oxide spacer
21
stuck to the sidewall of the poly gate
12
, an oxide liner
22
, and a nitride spacer
23
. As specifically indicated in this figure, the oxide liner
22
covers the offset oxide spacer
21
and its lower portion extends laterally to directly cover and borders the P
−
ultra-shallow junction S/D extension
32
.
The P
−
ultra-shallow junction S/D extension
32
is formed after the formation of the pair of offset spacers
21
through low-energy ion implantation. Using the gate
12
the offset spacers
21
as an implant mask, dopants h as boron are doped into the N well
16
of the silicon substrate to a depth such as for example 20 to 30 nanometers below the surface of the silicon substrate. A or laser annealing process is then carried out to activate the dopants trapped in the silicon crystal at 900 to 1000° C. in a few seconds.
However, the above-mentioned prior art PMOS transistor
10
encounters a bottleneck that the sheet resistance in the P
−
ultra-shallow junction S/D extension
32
cannot not be further reduced due to the fact that the active boron concentration in silicon substrate is limited by borons solid solubility thereof.
SUMMARY OF INVENTION
Accordingly, the primary object of the present invention is to provide a novel MOS transistor structure capable of reducing sheet resistance in the source/drain extensions.
It is another object of the present invention to provide an advanced MOS transistor structure having ultra-shallow junction source/drain extensions with active boron concentration that is greater than the maximum boron solid solubility in silicon within a certain junction depth.
To these ends, in one aspect of this invention, a MOS transistor includes a gate electrode formed on a semiconductor substrate, and a gate insulating layer formed between the gate electrode and the semiconductor substrate. A spacer is disposed on each sidewall of the gate electrode. A lightly doped source/drain (S/D) extension is formed in the semiconductor substrate under the spacer. The lightly doped S/D extension comprises a raised epitaxial layer bordering bottom of the spacer. A heavily doped S/D region is formed in the semiconductor substrate next to an outer edge of the spacer. A silicide layer is formed on the heavily doped S/D region. The epitaxial layer has a lattice constant that is greater than the lattice constant of single silicon crystal.
Other objects, advantages, and novel features of the claimed invention will become more clearly and readily apparent from the following detailed description when taken in conjunction with the accompanying drawings.


REFERENCES:
patent: 6246091 (2001-06-01), Rodder
patent: 6278165 (2001-08-01), Oowaki et al.
patent: 6323525 (2001-11-01), Noguchi et al.
patent: 6406973 (2002-06-01), Lee

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