MOS transistor having an offset region

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C257S335000, C257S340000, C257SE29023

Reexamination Certificate

active

07115946

ABSTRACT:
A semiconductor device includes a semiconductor region of a first conductivity type, a drain region of the first conductivity type, an offset region of the first conductivity type, a body region of the second conductivity type, a source region of the first conductivity type, a gate insulating film and a gate electrode. The drain region is provided in a surface of the semiconductor region and is shaped like a stripe. The offset region is provided in the surface of the semiconductor region and surrounds the drain region. The body region is provided in the surface of the semiconductor region and surrounds the offset region. The source region is provided in a surface of the body region and surrounds the offset region. The gate insulating film is provided on a part of the body region. The gate electrode is provided on the gate insulating film.

REFERENCES:
patent: 5747850 (1998-05-01), Mei
patent: 5932897 (1999-08-01), Kawaguchi et al.
patent: 6025237 (2000-02-01), Choi
patent: 2002/0050619 (2002-05-01), Kawaguchi et al.
patent: 10-321853 (1998-12-01), None
R. Zhu, V. Parthasarathy, J. Capilla, W. Peterson, M. Bacchi, M. Zunino, and R. Baird, “Suppression of Substrate Injection by RESURF LDMOS Dev.in a Smart Power Techn.for 20-30V Applications,” Proc. Bipolar/BiCMOS Circuits and Tech.,Mtg. (1998) pp. 184-186.
V.Parthasarathy, V. Khemka, R. Zhu, and A. Bose, SOA Improvement by a Double RESURF LDMOS Technique in a Power IC Technology, Proc. Int'l Electron Devices Mtg., (2000) pp. 4.2.1-4.2.4.
Zahir Parpia and C. Andre T. Salama, “Optimization of RESURF LDMOS Transistors: An Analytical Approach,” IEEE Trans. on Electron Devices, vol. 17, No. 3, (Mar. 1990), pp. 789-796.
S. Wolf, “Silicon Processing for the VLSI Era: vol. 2-Process Intergration,” Lattice Press, Sunset Beach, CA (1990), p. 390.
Yasuke Kawaguchi, et al., “A Low On-Resistance 60 V MOSFET High Side Switch and a 30 V npn Transistor Based on 5 V BiCMOS Process”, IEEE BCTM 9.3, 1997, pp. 151-154.
U.S. Appl. No. 11/261,531, filed Oct. 31, 2005, Nakamura et al.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

MOS transistor having an offset region does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with MOS transistor having an offset region, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and MOS transistor having an offset region will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3615584

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.