Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2006-05-16
2006-05-16
Brewster, William M. (Department: 2823)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S651000, C438S655000, C438S656000
Reexamination Certificate
active
07045456
ABSTRACT:
Methods are presented for fabricating transistor gate structures, wherein upper and lower metal suicides are formed above a gate dielectric. In one example, the lower silicide is formed by depositing a thin first silicon-containing material over the gate dielectric, which is implanted and then reacted with a first metal by annealing to form the lower silicide. A capping layer can be formed over the first metal prior to annealing, to prevent oxidation of the metal prior to silicidation, and a barrier layer can be formed over the lower silicide to prevent reaction with subsequently formed silicon material. In another example, the lower silicide is a multilayer silicide structure including a plurality of metal silicide sublayers.
REFERENCES:
patent: 4628588 (1986-12-01), McDavid
patent: 4641417 (1987-02-01), McDavid
patent: 4672419 (1987-06-01), McDavid
patent: 4954867 (1990-09-01), Hosaka
patent: 5633522 (1997-05-01), Dorleans et al.
patent: 5723893 (1998-03-01), Yu et al.
patent: 5937315 (1999-08-01), Xiang et al.
patent: 6103607 (2000-08-01), Kizilayalli et al.
patent: 6376342 (2002-04-01), Tseng
patent: 6410967 (2002-06-01), Hause et al.
patent: 6432817 (2002-08-01), Bertrand et al.
patent: 6482705 (2002-11-01), Yu
patent: 6602781 (2003-08-01), Xiang et al.
patent: 6617624 (2003-09-01), Powell
patent: 2003/0109121 (2003-06-01), Rotondaro
“Mo2N/Mo GAFP MOSFETs”, Manjin J. Kim and Dale M. Brown, IEEE, 1982, pp. 560-563.
“Application of MoSi2to the Double-Level Interconnections of I2L Circuits”, Yoshitaka Sasaki, Osamu Ozawa, and Shuichi Kamey Ama, IEEE Transactions on Electron Devices, vol. ED-27, No. 8, Aug., 1980, 5 pgs.
“Work Function Controlled Silicide Technology for Submicron CMOS”, Masakazu Kakumu and Kazuhiko Hashimoto, Source and date unknown, 2 pgs.
“Refractory Metal Silicide/N+ Polysilicon in CMOS/SOS”, B. C. Leung and J. S. Maa, Source and date unknown, 4 pgs.
“Fabrication of Mo-Gate/TI-Silicide-Clad-Moat MOS Devices by Use of Multilayer-Glass Depositions”, J. M. McDavid, IEEE Electron Device Letters, vol. EDL-5, No. 9, Sep., 1984, 2 pgs.
“Lightly Impurity Doped (LD) Mo Silicide Gate Technology”, Masakazu Kakumu and Jun'ichi Matsunaga, IEEE, 1985, pp. 415-418.
“An Investigation of Molybdenum Gate for Submicrometer CMOS”, Robert F. Kwasnick, Edmund B. Kaminsky, Paul A Frank, Gerhard A Franz, Kenneth J. Polasko, Richard J. Saia and Thomas B. Gorczya, IEEE Transactions on Electron Devices, vol. 35, No. 9, Sep., 1988, 7 pgs.
“Electrical Characteristics of TiB2for ULSI Applications”, Chang Sik Choi, Qingfeng Wang, Carlton M. Osburn, Gary A Ruggles and Ayan S. Shah, IEEE Transactions on Electron Devices, vol. 39, No. 10, Oct., 1992, pp. 2341-2345.
“Fin FET Process Refinements for Improved Mobility and Gate Work Function Engineering”, Yang-Kyu Choi, Leland Chang, Pushkar Ranade, Jeong-Soo Lee, Daewon Ha, Sriram Balasubramanian, Aditya Agarwal, Mike Ameen, Tsu-Jae King, and Jeffrey Bokor, IEEE, 2002, 4 pgs.
“Silicon Processing for The VLSI Era, vol. 2: Process Integration”,MOS Devices and NMOS Process Integration,Stanley Wolf PhD. 1990, 7 pgs.
“High Speed CMOS Structure with Optimized Gate Work Function”, T. Noguchi, Y. Asahi, M. Nakahara, K. Maeguchi and K. Kanzaki, Source and Ate not Available, 2 pgs.
Colombo Luigi
Murto Robert William
Visokay Mark Robert
Brady III W. James
Brewster William M.
Garner Jacqueline J.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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