MOS transistor and semiconductor integrated circuit

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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Details

C257S390000, C257SE29345, C365S072000

Reexamination Certificate

active

07847324

ABSTRACT:
A MOS transistor includes plural transistor cell blocks arranged adjacently in parallel to one another, wherein the plural transistor cell blocks are configured to have plural transistor cells, plural boundaries that are parallel to the plural transistor cells, and plural back gates arranged at the plural boundaries, each of the plural transistor cell blocks has two boundaries of the plural boundaries, wherein the plural transistor cells have a substantially striped shape, and each of the plural transistor cell blocks includes: at least one drain; plural sources; and plural extended gates, wherein each of the plural transistor cells is formed from one of the plural extended gates sandwiched by one of at least one drain and one of the plural sources, one of the plural sources is adjacent to one of two boundaries, and another one of the plural sources is adjacent to another one of two boundaries.

REFERENCES:
patent: 7623384 (2009-11-01), Iwata
patent: 7759720 (2010-07-01), Arigane et al.
patent: 2007/0262390 (2007-11-01), Ishida et al.
patent: 10-012824 (1998-01-01), None

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