MOS transistor and semiconductor device

Active solid-state devices (e.g. – transistors – solid-state diode – Gate arrays – Having specific type of active device

Reexamination Certificate

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Details

C257S776000, C257S758000, C257SE27108, C257SE21632

Reexamination Certificate

active

07977709

ABSTRACT:
According to one embodiment of the present invention, a MOS transistor includes a semiconductor layer including a source region, a drain region, and a channel region disposed between the source region and the drain region. A gate structure is arranged above the channel regions. A source wiring structure is arranged above the source region and is connected to the source region. A drain wiring structure is arranged above the drain region and is connected to the drain region. The width of the source wiring structure is larger than the width of the drain wiring structure, and the height of the source wiring structure is smaller than the height of the drain wiring structure, or vice versa.

REFERENCES:
patent: 2004/0140569 (2004-07-01), Meguro et al.
Knoblinger, G., et al., “A New Model for Thermal Channel Noise of Deep Submicron MOSFETs and its Application in RF-CMOS Design,” 2000 Symposium on VLSI Circuits, Digest of Technical Papers 2000, Jun. 15-17, 2000, pp. 150-153, IEEE, Los Alamitos, CA.
Nicolson, S. T., et al., “Methodology for Simultaneous Noise and Impedance Matching in W-Band LNAs,” IEEE 2006 Compound Semiconductor Integrated Circuit Symposium, CSIC 2006, Nov. 2006, pp. 279-282, IEEE, Los Alamitos, CA.
Khanpour, M., et al., “A High-Gain, Low-Noise, +6dBm PA in 90nm CMOS for 60-GHz Radio,” IEEE 2007 Compound Semiconductor Integrated Circuit Symposium, CSIC 2007, Oct. 14-17, 2007, pp. 1-4, IEEE, Los Alamitos, CA.
Weyers, C., et al. “Improved RF-Performance of Sub-Micron CMOS Transistors by Asymmetrically Fingered Device Layout,” Radio Frequency Integrated Circuits Symposium, 2008, pp. 563-566, IEEE.

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