Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-03-11
2003-05-13
Lee, Eddie (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S377000, C257S378000, C257S379000, C257S380000, C257S384000, C257S412000
Reexamination Certificate
active
06563179
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an MOS transistor. To increase the packing density of an integrated circuit configuration requires MOS transistors with channel lengths that are continually being made shorter. What is particularly problematic about miniaturization is short channel effects, which can be reduced by particularly flat source/drain zones.
This type of MOS transistor is described in European Patent Application EP 0268 941. The flat source/drain zones are created by dopant diffusion from overlying doped silicon layers. Source-drain terminals consisting of silicide are disposed on the silicon layers for the purpose of lowering the electrical resistance of the MOS transistor. The silicon layers serve both as the dopant source and as protection against shorts between the silicide source-drain terminals and the substrate. The silicon layers are created by selective epitaxy between a gate electrode of the transistor and field oxide regions that surround the transistor.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide an MOS transistor and a method for producing the transistor which overcome the above-mentioned disadvantages of the prior art apparatus and methods of this general type.
In particular, it is an object of the invention to provide an MOS transistor that exhibits fewer short channel effects and fewer leakage currents when compared to prior art MOS transistors, and wherein the capacitances formed by the source/drain zones and the substrate are smaller when compared to prior art MOS transistors.
With the foregoing and other objects in view there is provided, in accordance with the invention, a metal oxide semiconductor transistor that includes: a substrate having two doped regions located therein; a gate electrode configured on the substrate between the two doped regions; a gate dielectric separating the gate electrode from the substrate; two isolating separating layers of silicon nitride disposed on the substrate; conductive structures; and isolating structures. The gate electrode has two opposite lateral surfaces. Each one of the two opposite lateral surfaces of the gate electrode is provided with a respective one of the isolating structures. The gate electrode and the doped regions are configured between the two isolating separating layers. The two isolating separating layers are situated at a distance away from the gate electrode. The two doped regions have boundary surfaces. Each one of the boundary surfaces is located between the gate electrode and a respective one of the two isolating separating layers. Each one of the conductive structures is disposed on a respective one of the two isolating separating layers. Each one of the conductive structures laterally protrudes beyond the respective one of the two isolating separating layers to adjoin a respective one of the isolating structures and a respective one of the boundary surfaces.
In accordance with an added feature of the invention, the conductive structures consist substantially of doped silicon.
In accordance with an additional feature of the invention, the conductive structures consist substantially of doped silicon.
With the foregoing and other objects in view there is provided, in accordance with the invention, a method for producing a metal oxide semiconductor transistor, which includes steps of: forming a gate dielectric on a substrate; forming a gate electrode on the gate dielectric; subsequent to forming the gate electrode, forming spacing structures at two opposite lateral surfaces of the gate electrode; performing a nitridation step such that a layer of silicon nitride is formed on the substrate beneath the spacing structures but not on the spacing structures; forming first portions of conductive structures on exposed portions of the layer of silicon nitride by selectively epitaxially growing silicon; removing the spacing structures and portions of the layer of silicon nitride located beneath the spacing structures, thereby forming two separating layers from the layer of silicon nitride; providing at least each of the two opposite lateral surfaces of the gate electrode with a respective isolating structure; forming each one of the conductive structures on a respective one of the two separating layers such that each one of the conductive structures protrudes laterally beyond the respective one of the two separating layers beneath it, adjoins the isolating structure on a respective one of the two opposite lateral surfaces of the gate electrode, and adjoins a portion of the substrate that is located between the gate electrode and the respective one of the two separating layers; using the two separating layers and the gate electrode as masks while incorporating dopant into the substrate to form a first doped region in a portion of the substrate that adjoins the one of the conductive structures on one of the two separating layers and to form a second doped region in a portion of the substrate that adjoins the conductive structure on another one of the two separating layers; and forming second portions of the conductive structures by selectively epitaxially growing silicon.
In accordance with an added mode of the invention, the spacing structures are formed as spacers by depositing and etching-back a material.
In accordance with an additional mode of the invention, the step of incorporating the dopant into the substrate is performed by: doping the conductive structures with the dopant; and using the two separating layers as diffusion barriers while performing a tempering step such that a portion of the dopant diffuses into the substrate from the conductive structures to form the first doped region and the second doped region.
In accordance with another mode of the invention, the step of doping the conductive structures is performed by implanting the dopant with an energy such that a maximum concentration of the dopant occurs near the two separating layers.
In accordance with a further mode of the invention, the step of doping the conductive structures is performed in situ during a selective epitaxy step.
The objects of the invention are solved by providing an MOS transistor wherein a gate electrode is disposed on a substrate and is isolated therefrom by a gate dielectric. Each of at least two opposing lateral surfaces of the gate electrode is respectively provided with an isolating structure. The gate electrode is disposed between two doped regions that are disposed in the substrate. The gate electrode and the doped regions are disposed between two separating layers that are disposed on the substrate. A respective conductive structure is disposed on each of the insulating layers. Each conductive structure projects laterally beyond the underlying separating layer in such a way that it adjoins one of the isolating structures and the doped region that is disposed between the gate electrode and the separating layer.
The object of the invention is also solved by a method for producing an MOS transistor wherein a gate dielectric is created on a substrate. A gate electrode is created on the gate dielectric. Two separating layers are created on the substrate in such a way that the gate electrode is arranged between them and is separated away from them. At least two opposite side surfaces of the gate electrode are each provided with an isolating structure. On each of the separating layers, a conductive structure is created which protrudes laterally beyond the separating layer beneath it in such a way that it adjoins one of the isolating structures and a part of the substrate which is disposed between the gate electrode and the separating layer. In the parts of the substrate adjoining the conductive structures, two doped regions are created by incorporating dopant into the substrate, during which the separating layers and the gate electrode act as masks.
The doped regions are thus created between the gate electrode and the separating layers.
The doped regions can be connected by way of the conductive structures. The doped re
Fenty Jesse A.
Greenberg Laurence A.
Infineon Technologies
Lee Eddie
Locher Ralph E.
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