Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Patent
1998-02-23
1999-10-26
Hardy, David B.
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
257347, H01L 2701, H01L 310392
Patent
active
059733659
DESCRIPTION:
BRIEF SUMMARY
DESCRIPTION
1. Technical Field
This invention relates to a MOS (Metal-Oxide-Semiconductor) type field effect transistor made on an SOI (Silicon On Insulator) type substrate, i.e. a substrate comprising a thin film of silicon on a silicon oxide support.
The invention also relates to a preparation process for an SOI type substrate to delimit active regions of MOS transistors on this substrate.
The invention is used for applications in microelectronics for the manufacture of components and fast integrated circuits with low electrical consumption.
2. State of Prior Art
In general, fast MOS transistors, and fast two-pole transistors, require high power supply voltages and cause problems due to their high consumption of electrical energy. With the increase in the integration density, the distance between the source and drain is tending to reduce. This phenomenon creates leakage currents between the source and the drain in MOS transistors and these currents reduce the reliability of components due to the Joule effect.
Components made on a silicon on insulator (SOI) type substrate are used to insulate the source and drain from the substrate and reduce parasite capacitances firstly between the source and the substrate, and secondly between the drain and the substrate. This characteristic enables components to operate at a high frequency. Excessive doping under the source and drain is also avoided. However, MOS transistors on SOI substrate have a high electrical consumption due to leakage currents under low inversion conditions, i.e. when the voltage applied to them is low and the transistor circuit is in a waiting or standby state. It also generates a large amount of noise between the source and the drain.
Problems of checking the characteristics of transistors in low inversion become more obvious with reference to FIG. 1.
FIG. 1 shows a section through a MOS transistor of a known type made on SOI substrate.
The transistor, seen in a cross-sectional view, is made on an SOI substrate 10 comprising a buried silicon oxide layer 12 and a surface silicon film 14. An active region 14a of the transistor is formed in film 14. It is delimited laterally by thick blocks of silicon oxide 16.
To simplify the Figure, and due to its symmetry, only one side, and only one block 16 is shown in FIG. 1.
A grid 18 formed essentially above the active region 14a is separated from this active region by a thin layer of grid oxide 20. The transistor source and drain do not lie in the plane of the section in FIG. 1 and consequently are not shown in it.
Problems in checking the characteristic in low inversion of a transistor conform with FIG. 1 are caused by three main phenomena.
The first phenomenon is the sharing of charges between the channel itself and the flank of the transistor. A second phenomenon is perforation between the transistor source and drain. Finally, a third phenomenon described below, is the leakage of currents through the "bottom" of the active region.
The first two phenomena are classical and also occur for MOS transistors made on a solid silicon substrate.
Control problems related to these two phenomena may be solved by varying the design and doping of transistor flanks and by an appropriate design of the source and drain regions. For example, it would be possible to implant sources and drains such that they have a gradual profile while reducing lateral diffusion under the grid (LDD). Document (1), the reference of which is given at the end of this description, provides further information about this subject.
The third phenomenon is specific to MOS transistors made on an SOI substrate. Note that the leakage current through the "bottom" of the active region includes a leak directly between the active region 14a and the buried layer of silicon oxide 12 and a leak on the edge of the active region at the interface between the active layer 14a, the silicon oxide block 16 and the buried layer 12.
This interface is referred to as the "lower corner" throughout the rest of this description, and it is identified by reference 24 i
REFERENCES:
patent: 4523213 (1985-06-01), Konaka et al.
patent: 4635344 (1987-01-01), Havemann
patent: 5470781 (1995-11-01), Chidambarrao et al.
O. LeNeel et al., "Rounded Edge Mesa for Submicron SOI COMS Process", Proceedings of the European Solid State Device Research Conference (ESSDERC), pp. 13-14, Sep. 10, 1990.
S. Deleonibus et al., "A High Pressure High Temperature Poly Buffer LOCOS (HP-HTPBL) Isolation Process for 1Gbit Density Non Volatile Memories", International Conference on Solid State Devices and Materials, pp. 893-895, 1995.
S. Crowder et al., "Thermal Oxidation Kinetics and LOCOS Isolation in SOI Materials", Proceedings of the International SOI Conference, Ponte Verde Beach, Fl., Oct. 6-8, 1992, pp. 24-25.
Commissariat a l''Energie Atomique
Eckert II George C.
Hardy David B.
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