Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-01-17
2003-01-14
Wojciechowicz, Edward (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S335000, C257S362000, C257S375000, C257S401000
Reexamination Certificate
active
06507080
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a metal-oxide-semiconductor (MOS) transistor and, more specifically, to a complementary MOS (CMOS) transistor, such as for a power switch.
2. Description of the Related Art
MOS transistors and, more particularly, CMOS transistors are utlizied for a variety of applications, including power switches. In fact, one of the most fundamental factors of a power integrated circuit is a bridge circuit, in which pull-up and pull-down transistors selectively switch a load node in the opposite directions to each other. The related general structure is an H-bridge circuit where two points connected to the load are connected to a half-bridge circuit. The half-bridge circuit is used particularly in the control of a motor because the current is driven in either of the two opposite directions. Generally, a power integrated circuit includes an N-channel power field effect transistor (FET), for example a VDMOS device, in the driver circuit. Use is typically made of a MOS transistor, e.g., a complementary MOS transistor, for the power switch for the driver circuit of a power FET, especially a high-side driver.
MOS transistors, including CMOS transistors, preferably have a high breakdown voltage and resist parasitic operation. For example, the complementary MOS transistor used for the high-side driver must have a sufficiently high breakdown voltage and avoid parasitic operation to provide proper switching.
SUMMARY OF THE INVENTION
It is an object of the present invention to increase the withstand voltage of a MOS transistor.
It is another object of the present invention to prevent the parasitic operation of the MOS transistor.
The present invention therefore employs a twin-well structure in order to increase the withstand voltage of the MOS transistor and has a sink region to prevent parasitic operation. In one aspect of the present invention, there is provided a MOS transistor including a semiconductor layer; first and second wells of different conductivity types formed in the semiconductor layer; source and drain regions formed in the first and second wells, respectively; and a gate formed on the semiconductor layer.
The MOS transistor of this aspect of the present invention can further include a sink region formed in the semiconductor layer and surrounding the first and second wells, and an isolation layer formed in the semiconductor layer and disposed opposite to the first and second wells with respect to the sink region.
Preferably, the respective junction depths of the first and second wells are different from each other.
In another aspect of the present invention, there is provided a MOS transistor including a semiconductor substrate of a first conductivity type; a semiconductor layer of a second conductivity type formed on the semiconductor substrate; a sink region of the second conductivity type formed in the semiconductor layer and heavily doped relative to the semiconductor layer; source and drain regions formed in the semiconductor layer and surrounded with the sink region; and a gate formed on the semiconductor layer.
The MOS transistor of this aspect of the present invention can further include a buried layer of the second conductivity type formed between the semiconductor substrate and the semiconductor layer and heavily doped relative to the semiconductor layer. First and second wells of different conductivity types are formed in the semiconductor layer and include the source and drain regions, respectively. Preferably, the source and drain regions have the second conductivity type, and the first and second wells have the first and second conductivity types, respectively. The MOS transistor further of this aspect of the present invention can also include a bulk region formed in the first well and having the same conductivity type as the first well.
A method for fabricating such a MOS transistor is also provided that includes the steps of forming a buried layer of a second conductivity type and a base layer of a first conductivity type on a semiconductor substrate of the first conductivity type; growing a semiconductor layer on the semiconductor substrate; forming a sink region of the second conductivity type in a portion of the semiconductor layer; forming a first well of the first conductivity type in a portion of the semiconductor layer overlying the buried layer and a first isolation region of the first conductivity type in a portion of the semiconductor layer overlying the base layer; forming a second well of the second conductivity type in a portion of the semiconductor layer; forming a gate oxide layer and a gate electrode on the semiconductor layer; and forming source and drain regions in the first and second wells, respectively.
REFERENCES:
patent: 5844275 (1998-12-01), Kitamura et al.
patent: 6093620 (2000-07-01), Peltzer
Jang Kyung-Oun
Lee Sun-Hak
Fairchild Korea Semiconductor Ltd.
Wojciechowicz Edward
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