MOS transistor

Details MOS transistor MOS transistor

2006-09-05

2006-09-05

Nelms, David (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S310000, C438S197000

Reexamination Certificate

active

07102183

ABSTRACT:
In P-channel MOS transistor comprising a gate insulating film composed of a high dielectric constant material and the gate electrode composed of polycrystalline silicon, a technology for preventing Fermi level pinning and providing a stable reduction of the threshold voltage is provided. The MOS transistor functions as a buried channel transistor formed by implanting In as a P-type impurity into the channel region. In addition, the gate electrode is composed of the polycrystalline silicon film, which is doped with N-type impurity. Thus, the gate depletion caused by Fermi level pinning can be effectively inhibited. Therefore the depletion in the gate electrode can be avoided and the threshold voltage can be stably diminished. In this case, the threshold voltage is stably reduced since electric charge is induced by applying a constant voltage to the gate electrode.

REFERENCES:
patent: 5374836 (1994-12-01), Vinal et al.
patent: 5698884 (1997-12-01), Dennen
patent: 5952701 (1999-09-01), Bulucea et al.
patent: 6448192 (2002-09-01), Kaushik
patent: 2003-289140 (2003-10-01), None
“Fermi Level Pinning at the Polysi/Metal Oxide Interface”, C. Hobbs et al., 2003 Syposium on VLSI Technology Digest of Technical Papers, 4-89114-035-6/03.

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