MOS transistor

Details MOS transistor MOS transistor

2003-01-08

2004-08-24

Smith, Matthew (Department: 2825)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having schottky gate

C438S167000, C438S197000, C438S574000, C438S579000, C438S302000, C438S303000, C438S525000, C438S666000, C257S133000, C257S134000, C257S282000, C257S283000, C257S350000

Reexamination Certificate

active

06780694

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to field-effect transistor having T-shaped gate electrodes.
2. Description of Related Art
The ever smaller dimensions of FET devices have led to the employment of T-shaped gate electrodes. State of the art MOS transistors are fabricated by depositing the gate stack material over the gate oxide and substrate. Lithography and etching processes are used to define the polysilicon gate structures. Next the gate structure and silicon substrate are thermally oxidized. After this, source/drain extensions are implanted. Sometimes the implant is performed using a spacer to create a specific distance between the gate and the as implanted junction. In some instances the S/D extensions for the NFET device will be implanted with no spacer and the PFET S/D extensions will be implanted with a spacer present. A thicker spacer is typically formed after the S/D extensions have been implanted. The deep S/D implants are then performed with the thick spacer present. High temperature anneals are done to activate the junctions after which the S/D and silicides are formed on the top surface of the gate electrode.
Generational improvements for high performance CMOS are obtained by decreasing the transistor line width (L poly), reducing the gate oxide thickness, and decreasing the S/D extension resistance. Smaller L poly results in less distance between source and drain. This results in faster switching speeds for CMOS circuits. However as the L poly gets smaller, the overall area available for silicidation is reduced. This means that as L poly shrinks, line resistance is increased. Increased line resistance causes degradation in device performance.
Drive currents for MOS devices are inversely proportional to gate oxide thicknesses. Thinner gate oxides yield higher drive currents. One problem with this is that as the gate oxide is thinned, polysilicon depletion effects become more pronounced. Polysilicon depletion is an effective thickening of the gate oxide.
One method of minimizing this problem is to employ gate predoping. In this technique the blanket polysilicon-Si is implanted prior to gate patterning. The problem with the predoping method is that etching and gate profiles are difficult to control.
S/D extension resistance is another important performance factor. Drive currents can be increased by reducing S/D extension resistance. Increasing the S/D extension dose leads to lower resistance but has the unwanted side effect of increasing the junction depth. One method for overcoming this problem is to implant the extension first with no spacer present and then form a thin spacer and perform a second implant. Alternatively, a notched gate may be used to perform this task by implanting at two or more angles. The drawback to the first method is increased process complexity, while the drawback to the second method is that notched gates typically have reduced line width control.
U.S. Pat. No. 4,679,311 of Lakhani et al. entitled “Method for Fabricating Self-Aligned Field-Effect Transistor Having T-Shaped Gate Electrode, Sub-Micron Gate Length and Variable Drain to Gate Spacing” relates to a dual gate MESFET (Metal Semiconductor Field Effect Transistor) formed on a compound semiconductor substrate composed of a material such as GaAs, InP, GaAlAs, etc. Lakhani et al. teaches a method of creating a “T” structure by using laminations of various metals to form multilayered metal stack. Subsequently, the lower lamination is etched selectively to form an undercut with respect to the upper laminations to create a “T-Shaped” structure. The preferred materials of the metallic laminations are Al, Ti, and Pt and the selective etch is performed using NaOH a chemistry. In one embodiment, the source and drain electrodes are formed by an angle deposition technique.
U.S. Pat. No. 6,284,613 of Subrahmanyam et al. entitled “Method for Forming a T-gate for Better Salicidation” describes a complex method of forming a “T” gate structure by using a damascene technique in conjunction with an additional lithographic mask step. The method does not allow for improved gate activation.
U.S. Pat. No. 6,107,667 of An et al. entitled “MOS Transistor with Low-k Spacer to Suppress Capacitive Coupling Between Gate and Source/Drain Extensions” describes a method for making a MOSFET, which includes establishing a void in a thick field oxide layer on a silicon substrate. Then sidewall spacers are formed adjacent to sidewalls of the void, exposed portions of a gate oxide layer at the bottom of the void are removed. Then a high-k gate insulator is formed at the base of the void and the remainder of the void is filled with a first portion of a gate electrode so that the high-k gate insulator is sandwiched between the gate electrode and the substrate. Next the spacers and the extension of a previously formed gate oxide layer are stripped away exposing the sidewalls of the initial gate electrode. A protective layer is formed on the sidewalls of the initial gate electrode and the now exposed walls of the void. Then the space remaining within the void is filled with, a low-k gate spacer inside the protective layer. Then a conductive cap is formed over the initial gate and the gate spacer (completing a T-shaped gate) The conductive cap extends directly above the source and drain extensions of the MOSFET. In summary, the An patent teaches a method of fabricating low-k dielectric constant spacers by using a replacement gate technique. The low-k spacers are recessed and a “T” shaped gate is formed by a deposition and etch back procedure. The invention does not teach a method of simultaneously improving gate activation, extension resistance, and decoupled source drain silicidation from gate silicidation.
U.S. Pat. No. 6,239,007 Wu entitled “Method of Forming T-Shaped Gate” describes a method of forming a T-shaped gate by sequentially forming a first conformal insulation layer over an initial gate structure and then forming a second insulation layer thereover, with the first insulation layer having a faster etching rate for a given etchant. Planarization of the second insulation layer exposes part of the first insulation layer by etching with the given etchant to remove the first insulation layer sufficiently to expose the top of the initial gate structure. A conductive layer is then formed over the exposed gate structure and planarized out so that only the portion of conductive layer above the gate structure remains. The insulation layers are removed using the conductive layer above the gate structure as an etching mask leaving spacers alongside the initial gate structure. A silicide process is carried out to form a silicide layer over the conductive layer and over the semiconductor substrate, but neither a source region nor a drain region is shown. Wu teaches a method of forming a “T” gate structure by depositing a conformal film on top of a patterned gate stack. A dielectric material is deposited and planarized to the top of the covered gate. The conformal film is removed and a conductive material is deposited and planarized to form the “T” structure. This invention does not teach a method of simultaneously improving gate activation, extension resistance, and decoupled source drain silicidation from gate silicidation as our invention does.
U.S. Pat. No. 6,159,781 of Pan et al. entitled “Way to Fabricate the Self-Aligned T-Shape Gate to Reduce Gate Resistivity” describes a method of fabricating a semiconductor field effect transistor, wherein the gate has a short foot portion in contact with the semiconductor substrate for a short gate length and consequent low capacitance, and a large amount of metal in a contact portion for low gate resistance. Salicides are formed on the T-gate source on drain contact areas resulting in large, low resistance contact areas. Trench insulation regions are formed within a semiconductor substrate. A blanket dielectric layer is deposited over the device and then a first trench is etched within the dielectric layer leaving a dielectric depth of d

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