Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-03-14
2003-03-18
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S327000, C257S335000, C257S337000, C257S344000, C257S346000, C438S276000, C438S217000
Reexamination Certificate
active
06534827
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same. In particular, the present invention relates to a MOS transistor having a medium withstand voltage structure with a withstand voltage of 8 to 30 volts.
2. Description of the Related Art
Conventionally, as shown in
FIG. 11
, a lightly doped drain (“LDD”) structure is known, which is composed of a gate oxide film
102
and a polycrystalline silicon gate electrode
104
having side spacers
103
on both sides, formed on a silicon semiconductor substrate
101
, low-concentration diffusion layers
105
formed on the surface of the substrate
101
, positioned below the side spacers
103
, high concentration diffusion layers
106
called a source and a drain formed on the surface of the substrate
101
on both sides of the gate electrode
104
, and a channel region
107
between the source and the drain.
A MOS transistor having the above-mentioned conventional LDD structure has the following problems. The width of each side spacer is very small, and hence, the width of each impurity concentration region (i.e., the low-concentration diffusion layer
105
) is also small, so that a withstand voltage of 8 to 30 volts cannot be obtained. Furthermore, the capacitance between the source/drain region and the gate electrode cannot be decreased. The ends of the source and drain regions (i.e., the high impurity concentration regions) are terminated at field oxide films, so that a junction withstand voltage between the source/drain region and a channel stop layer under the field oxide film is also low. Still furthermore, it is difficult to form MOS transistors having a plurality of withstand voltages on the identical substrate.
SUMMARY OF THE INVENTION
Therefore, with the foregoing in mind, it is an object of the present invention to provide a plurality of medium withstand voltage MOS transistors having different withstand voltages of 8 to 30 volts on the identical substrate by a simple process without increasing the number of masks to be used, wherein a high drain withstand voltage, a small capacitance between a source/drain region and a gate electrode, and a high junction withstand voltage between a channel stop layer under a field oxide film and a source/drain region can be obtained (which cannot be achieved by a MOS transistor having a conventional LDD structure), and the drain withstand voltage can be controlled
In order to achieve the above-mentioned object, the following means are used in the present invention.
(1) The semiconductor device is characterized by including: a field oxide film formed on a semiconductor substrate of one conductivity; a gate electrode formed on the semiconductor substrate via a gate oxide film; source and drain regions of reverse conductivity with low concentration, surrounded by the field oxide film and the gate electrode; an interlayer film for electrically insulating the gate electrode, the source and drain regions, and a wiring formed thereon; and a contact hole for electrically connecting the wiring, the gate electrode, and the source and drain regions, wherein only a portion of the source and drain regions opened to the contact hole is selectively formed into a diffusion layer of reverse conductivity with high concentration.
(2) The semiconductor device is characterized in that an impurity concentration of the source and drain regions is 1E16 to 1E18 atoms/cm
3
.
(3) The semiconductor device is characterized in that an impurity concentration of the diffusion layer is 1E19 to 5E20 atoms/cm
3
.
(4) The semiconductor device is characterized in that a width of the source and drain regions is varied by changing a distance between one end of the gate electrode and one end of the diffusion layer, whereby a plurality of MOS transistors having different withstand voltages are formed on an identical substrate.
(5) The method of manufacturing a MOS transistor having an medium withstand voltage structure is characterized by including the steps of: forming a gate insulating film on a surface of a semiconductor substrate; patterning a gate electrode on the gate insulating film; forming a low concentration diffusion region by ion-implanting impurities into the surface of the semiconductor substrate, using the gate electrode as a mask; forming an interlayer film containing impurities over an entire surface of the semiconductor substrate, and flattening the interlayer film by heat treatment; selectively etching the interlayer film to form contact holes in the low concentration diffusion region and the gate electrode; forming a high concentration diffusion region by ion-implanting impurities into the surface of the semiconductor substrate, using the contact hole as a mask; conducting heat treatment; forming a metal material over an entire surface of the semiconductor substrate by vacuum evaporation or sputtering, and then patterning the metal material by photolithography and etching; and covering an entire surface of the semiconductor substrate with a surface protective film.
(6) The method is characterized in that the interlayer film containing impurities is a BPSG interlayer film.
(7) The method is characterized in that the heat treatment after implanting the impurities into the surface of the semiconductor substrate is conducted at 800° C. to 1050° C. within 3 minutes so as to activate the impurities, whereby the high concentration diffusion region is formed.
(8) The method of manufacturing a MOS transistor is characterized by including the steps of: forming a gate insulating film on a surface of a semiconductor substrate; patterning a gate electrode on the gate insulating film; forming a low concentration diffusion region by ion-implanting impurities into the surface of the semiconductor substrate, using the gate electrode as a mask; forming an interlayer film containing impurities over an entire surface of the semiconductor substrate, and flattening the interlayer film by heat treatment; selectively etching the interlayer film to form contact holes in the low concentration diffusion region and the gate electrode; forming polycrystalline silicon over an entire surface of the semiconductor substrate by a CVD method, and then implanting phosphorus as an impurity element at high concentration by ion implantation or by using an impurity diffusion furnace; patterning the polycrystalline silicon by photolithography and etching; diffusing the impurities in the polycrystalline silicon into the surface of the semiconductor substrate by heat treatment to form a high concentration diffusion region; forming a metal material over an entire surface of the semiconductor substrate by vacuum evaporation or sputtering, and then patterning the metal material by photolithography and etching; and covering an entire surface of the semiconductor substrate with a surface protective film.
(9) The method is characterized in that the interlayer film containing impurities is a BPSG interlayer film.
(10) The method is characterized in that the heat treatment for diffusing the impurities in the polycrystalline silicon is conducted at 800° C. to 1050° C. within 3 minutes so as to activate the impurities, whereby the high concentration diffusion region is formed.
(11) The semiconductor device is characterized by including: a field oxide film formed on a semiconductor substrate of one conductivity; a gate electrode formed on the semiconductor substrate via a gate oxide film; source and drain regions of reverse conductivity, surrounded by the field oxide film and the gate electrode, wherein a concentration profile of the source and drain regions is arbitrarily varied by changing a region where impurities are implanted and a region where impurities are not implanted; an interlayer film for electrically insulating the gate electrode, the source and drain regions, and a wiring formed thereon; and a contact hole for electrically connecting the wiring, the gate electrode, and the source and drain regions.
(12) The semiconductor device is characterized in that
Osanai Jun
Shiiki Mika
Adams & Wilks
Nelms David
Seiko Instruments Inc.
Tran Mai-Huong
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