MOS switch that reduces clock feed through in a switched capacit

Details MOS switch that reduces clock feed through in a switched capacit MOS switch that reduces clock feed through in a switched capacit

1997-05-19

1999-05-04

Whitehead, Jr., Carol

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257298, 257320, 257346, 257300, H01L 2976

Patent

active

059006579

ABSTRACT:
The accumulation of a small positive charge on the source of a MOS switch which occurs after the switch has been turned off due to the parasitic capacitance that exists between the gate and the source of the transistor, known as clock feedthrough, is reduced by utilizing a split-gate MOS transistor, and by continuously biasing one of the gates of the split-gate transistor.

REFERENCES:
patent: 4794565 (1988-12-01), Wu et al.
patent: 5080317 (1998-09-01), Kuo
patent: 5115288 (1992-05-01), Manley
patent: 5461242 (1995-10-01), Muroaka et al.
patent: 5583810 (1996-12-01), Van Houdt et al.
patent: 5665987 (1997-09-01), Muroaka et al.
P.E. Allen et al., "CMOS Analog Circuit Design", Oxford University Press, Chap. 5, pp.204-211, (1987).

Affiliated with

Also associated with

Rating

MOS switch that reduces clock feed through in a switched capacit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with MOS switch that reduces clock feed through in a switched capacit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and MOS switch that reduces clock feed through in a switched capacit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1871239