MOS structure with hot carrier reduction

Details MOS structure with hot carrier reduction MOS structure with hot carrier reduction

1995-01-18

1997-01-28

Meier, Stephen

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257301, 257336, 257409, 257500, 257344, H01L 27108, H01L 2976, H01L 2994, H01L 2900

Patent

active

055980210

ABSTRACT:
An MOS structure is disclosed which is provided with a trench in the substrate adjacent the channel region of the substrate, i.e., adjacent the area of the substrate over which the gate oxide and gate electrode are formed. The region of the substrate beneath the trench is lightly doped to provide a deeper LDD region in the substrate between the channel and the drain region so that electrons traveling through the channel to the drain region follow a path deeper in the substrate and farther spaced from the gate oxide in the region of the substrate between the source region and the drain region where high fields are encountered by electrons traveling through the channel from the source region to the drain region.

REFERENCES:
patent: 4987089 (1991-01-01), Roberts
patent: 5047820 (1991-09-01), Garnett
patent: 5254866 (1993-10-01), Ogoh
patent: 5319231 (1994-06-01), Yamazaki et al.
patent: 5356828 (1994-10-01), Swan et al.
patent: 5360753 (1994-11-01), Park et al.
patent: 5372957 (1994-12-01), Liang et al.
Chang et al., "High-Voltage FET Integrated Circuit Process," IBM Technical Disclosure Bulletin, vol. 16, No. 5, Oct. 1973, pp. 1635-1636.
Sze, Semiconductor Devices: Physics and Technology, 1985, pp. 216-219.

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