MOS static type RAM having a variable load

Details MOS static type RAM having a variable load MOS static type RAM having a variable load

1985-06-03

1988-07-26

Hecker, Stuart N.

Static information storage and retrieval

Read/write circuit

For complementary information

365154, 365156, 365202, G11C 500, G11C 506, G11C 700

Patent

active

047605618

ABSTRACT:
An MOS static type RAM has a memory cell array comprising a plurality of static type memory cells arranged in matrix, a plurality of data lines connected to the data input-output terminals of the respective memory cells and a plurality of word lines connected to the selection terminals of the respective memory cells. Data line load circuits are disposed between the power terminal of the circuit and the data lines. Each data line load circuit is kept at a relatively high impedance in the data write-in operation, and at a relatively low impedance in the data read-out operation. The use of the data line load circuits comprised of such variable impedance circuits can speed up the operating speed of the RAM and can accomplish lower power consumption.

REFERENCES:
patent: 4300213 (1981-11-01), Tanimura et al.
patent: 4377856 (1983-03-01), Roesner
patent: 4386419 (1983-05-01), Yamamoto

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