Static information storage and retrieval – Read/write circuit – For complementary information
Patent
1994-09-09
1996-10-15
Zarabian, A.
Static information storage and retrieval
Read/write circuit
For complementary information
365208, G11C 700
Patent
active
055661262
ABSTRACT:
A MOS static memory device is provided in which transfer gates are connected between a bit line and one terminal of a sense amplifier and between a bit-bar line and the other terminal of the sense amplifier, respectively. The bit line and the bit-bar line are thereby separated from the sense amplifier during the read sensing. In addition, the sensing by the sense amplifier is started after the transfer gates are turned OFF, whereby the amount of potential change of the bit line and the bit-bar line is prevented from increasing. As a result, in a read operation, only a small potential difference is generated between the bit line and the bit-bar line in accordance with the stored contents of the memory cell, and little current for charge and discharge flows. Alternatively, the transfer gates are constructed in such a manner that first transfer gates with a lower ON resistance and second transfer gates with a relatively high ON resistance are connected in parallel. Due to this construction, during the ON period of the second transfer gates, the bit line and the bit-bar line are slightly supported by the sense amplifier. Accordingly, it is possible to obtain a sense amplifier occupying a smaller area and having a strong resistance against the bit-line interference.
REFERENCES:
patent: 4563754 (1986-01-01), Aoyama
patent: 4829483 (1989-05-01), Ogihara
patent: 4980863 (1990-12-01), Ogihara
patent: 5038324 (1991-08-01), Oh
patent: 5228106 (1993-07-01), Ang
patent: 5369622 (1994-11-01), McLaury
Sasaki et al., "A 23-ns 4-Mb CMOS SRAM with 0.2 .mu.A standby current" IEEE Journal of Solid-State Circuits (1990) 25(5):1075-1081. This publication is also cited on p. 1, lines 19-22 of the application as originally filed.
Sharp Kabushiki Kaisha
Zarabian A.
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