MOS semiconductor memory device

Details MOS semiconductor memory device MOS semiconductor memory device

1989-07-19

1991-07-09

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Including reference or bias voltage generator

365185, 365203, G11C 700

Patent

active

050311484

ABSTRACT:
In a memory MOS semiconductor memory device comprising a memory matrix having semiconductor memory elements arranged in rows and columns, the memory elements in the same rows being connected to the respective word lines, and the memory elements in the same columns being connected to the respective source lines and data lines. A row decoder outputs a row selection signal to one of the rows of the memory elements through the word lines, while a column decoder outputs a column selection signal to one of the columns through the source lines. A common data line is electrically coupled to a plurality of the data lines, a constant voltage is applied from a common circuit to the data lines through the common data line, and the current required for maintaining the common data line at a constant voltage is detected by a detecting circuit.

REFERENCES:
patent: 4387447 (1983-06-01), Klaas et al.
patent: 4709352 (1987-11-01), Kitazawa
patent: 4722075 (1988-01-01), Kaszubinski
1988 IEEE International Solid-State Circuits Conference, "Session X: Nonvolatile Memories, THAM 10.1: A 90ns 4Mb CMOS EPROM," by Canepa et al, Feb. 18, 1988, pp. 120-121.
M. Fukuda et al., "A 55ns 64Kx16b CMOS EPROM", 1988 IEEE International Solid-State Circuits Conference, Digest of Technical Papers, pp. 122-123.

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