Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1998-09-30
2002-05-07
Lee, Eddie (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S285000, C257S395000, C257S396000, C257S397000, C257S513000, C257S519000, C257S545000, C257S610000, C257S611000
Reexamination Certificate
active
06384455
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates in general to semiconductor technologies and, in particular, to complementary metal oxide semiconductor integrated circuit (CMOS IC) devices and manufacturing methods thereof. More particularly, but not exclusively, this invention relates to a method of controllably forming a well impurity profile at or near well boundaries or interfaces in semiconductive substrates.
BACKGROUND OF THE INVENTION
An explanation will first be given of problems faced with prior known well-region formation technologies in conjunction with one typical case of a CMOS integrated circuit (IC) device. The explanation begins with a brief description of some major process steps in the manufacture of such CMOS IC including element isolation and well formation procedures with reference to
FIGS. 1
to
5
.
Referring to
FIG. 1
, a substrate
101
has its surface on which a buffer oxide film
102
is formed to a thickness of, for example, 35 nanometers (nm). In this case the substrate
101
may be of either N type or P type. Then, a first stopper layer
103
is deposited by chemical mechanical polishing (CMP) techniques on the buffer oxide film
102
. The stopper
103
is made of a chosen material less in polishing rate than oxide films, such as SiN or polycrystalline silicon (polysilicon). Next, a mask layer (not shown) is deposited such as tetraethylorthosilicate (TEOS) oxide film or the like.
The resultant structure is coated with a resist layer (not shown) on the mask layer, which resist is then subject to patterning in a way such that the resist is partly removed away in selected regions in which grooves, called “trenches”
104
, are to be formed. Subsequently, the mask material is selectively removed. Thereafter, the resist is peeled off for sequential etching of the first stopper
103
and buffer oxide film
102
in this order; further, trenches
104
are formed in the substrate
101
as shown in FIG.
1
.
Then, as shown in
FIG. 2
, the inner walls of each trench
104
are oxidized, causing an oxide film
105
of TEOS or the like to be deposited within the trench
104
, thereby providing a buried oxide film. And, a chosen material that is low in polishing rate is deposited, which is then selectively removed at locations other than certain regions in which the trenches
104
of large area exist, to thereby form a second stopper layer. Note that the second stopper material is not depicted herein in view of the fact that such will not be required when the large-area trenches are absent. Thereafter, the resulting device structure is subject to surface planarization using CMP techniques.
Then, as shown in
FIG. 3
, the first stopper layer
103
is peeled off.
Then, as shown in
FIG. 4
, a well region of N type conductivity (N-well)
106
is formed in a substrate region in which a P-type transistor is to be formed, whist a P-type well (P-well)
107
is defined in a region selected for formation of an N-type transistor therein. Ion implantation is then performed with respect to those regions that will become channels in such a way as to permit each transistor to have a desired electrical characteristics. When this is done, the impurity profile is controlled in a way as will be described later.
After the buffer oxide film
102
is removed away from the overall surface of the substrate
101
, a gate oxide film
108
is formed on the surface of substrate
101
; then, a gate electrode
109
is formed thereon. Subsequently, ion implantation is done, forming a lightly doped drain (LDD) (not shown) in the surface of the substrate
101
. After sidewalls
110
are formed, ion implantation and thermal processing are carried out, forming diffusion layers
111
and
112
.
Then, as shown in
FIG. 5
, a dielectric film
113
made of SiO2 or the like is deposited as a first interlayer film. This dielectric film
113
is selectively removed in those regions for use in forming contact holes for electrical interconnection. Here, a first lead wire pattern
114
is formed, which may be a chosen conductive material.
Thereafter, second and third interlayer dielectric films may be formed along with chip lead patterns where necessary, although these are not depicted herein. After formation of these lead patterns, a protective film
115
made of SiN or the like is formed overlying the resultant surface, to thereby complete a CMOS IC device.
An explanation will next be given of the element isolation breakdown voltage at well boundaries as well as a scheme for maintaining the breakdown voltage.
FIGS. 6
to
8
are diagrams each illustrating, in cross-section, the well structure near the boundary of a well region of the CMOS IC as manufactured through the process steps shown in
FIGS. 1-5
. Parts or components identical to those of
FIG. 5
are designated by identical reference numerals, and an explanation thereof will be omitted herein.
Suppose that in the state shown in
FIG. 6
, a bias voltage VN of the positive polarity is applied to a heavily doped N type (N+ type) diffusion layer
112
in a P-well
107
while the N-well
106
and P-well
107
are biased at zero volts. In this case, the junction between N+-diffusion layer
112
and P-well
107
is in the “reverse” direction, wherein no currents attempt to flow therein. However, as the bias voltage VN increases in potential value, a depletion layer
117
between the N+-diffusion layer
112
and P-well
107
behaves to expand toward the P-well
107
, as designated by arrow “A” in FIG.
6
.
Then, as shown in
FIG. 7
, the P-well
107
laid between the N+-diffusion layer
112
and N-well
106
is fully depleted. When this is done, punch-through can take place between the N+ diffusion
112
and N-well
106
, causing a current to flow in the direction denoted by arrow C
1
. The potential value of bias voltage VN at this time is called the “isolation breakdown” voltage among those skilled in the semiconductor art.
Obviously, the isolation breakdown voltage must be significant relative to the power supply voltage used. To potentially increase the breakdown voltage, it should be required that the trench increase in depth lengthening the isolation/separation distance (denoted by arrow B
1
in FIG.
6
); or alternatively, the P-well
107
is required to increase in impurity concentration thereby limiting the expansion of the depletion layer
117
. Note here that an approach for increasing the trench width in order to lengthen the separation distance is not preferable in view of the integration density; accordingly, this approach is not practiced excessively. For example, assume that the trench depth is 0.7 micrometers (&mgr;m), the separation width is 0.4 &mgr;m, and the power supply voltage used is 3.3 volts. If this is the case, impurity concentration might be designed permitting a peak concentration of 1.0 to 5.0×10
17
atoms per cubic centimeter (cm-3) to appear at or near the bottom of each trench—namely at the depth of 0.8 to 0.9 &mgr;m).
Next, consider that the N-well
106
is biased at VNW (positive bias voltage) whereas the N+-diffusion layer
112
within P-well
107
and the P-well
107
are kept at zero volts, as shown in FIG.
8
. In this case, a multilayer structure consisting of the N-well
106
and buried oxide film
105
plus P-well
107
is equivalent to the gate/gate-oxide/P-well structure in N type MOS (NMOS) devices, wherein upon biassing of the N-well
106
, certain part of the P-well
107
along the trench side surface acts to invert as shown by wavy line D in
FIG. 8
, forming a channel. Thus, a current attempts to flow in the direction designated by arrow C
2
. This results in operation of a vertical-structured parasitic MOS transistor. When this is done, the effective separation distance designated by arrow B
2
in
FIG. 8
decreases, lowering the isolation breakdown voltage accordingly.
More specifically, when comparing the case of biasing the N+ diffusion layer
112
within the P-well
107
to the case the N-well
106
is biased, the latter tends to exhibit a decrease in
Kabushiki Kaisha Toshiba
Lee Eddie
Warren Matthew E.
LandOfFree
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