MOS semiconductor device with memory cells each having storage c

Details MOS semiconductor device with memory cells each having storage c MOS semiconductor device with memory cells each having storage c

1995-04-11

1997-06-10

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Including reference or bias voltage generator

365149, 36523003, 365205, G11C 700

Patent

active

056383290

ABSTRACT:
A MOS dynamic random access memory includes a plurality of pairs of bit lines, and word lines transverse to the bit lines to define cross points, at which an array of memory cells are arranged. Each cell has a storage capacitor and a transfer gate MOS transistor having a gate electrode coupled to a word line and being connected between the capacitor and a bit line. Sense amplifier circuits are connected to the bit line pairs, and have a first and a second common source line. A decoder and a word line driver are connected to the word lines. AMOS transistor is connected between the power supply voltage and the first common source line, for selectively supplying it with a first voltage which potentially defines a high-level voltage for the bit line pairs. A voltage generator is connected through a MOS transistor to the second common source line, for generating a second voltage which potentially defines a low-level voltage for the bit line pairs, and which is selectively supplied to the second common source line. The second voltage is greater in potential than the ground potential, which is employed as a source voltage.

REFERENCES:
patent: 4907199 (1990-03-01), Dosaka et al.
patent: 5278786 (1994-01-01), Kawauchi et al.

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