MOS Semiconductor device

Details MOS Semiconductor device MOS Semiconductor device

2002-09-25

2004-02-10

Wilson, Allan R. (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S330000, C257S332000

Reexamination Certificate

active

06690061

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2001-293928, filed on Sep. 26, 2001, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor devices. In particular, the present invention relates to a semiconductor device including a plurality of MOS transistors, drains of which are commonly connected.
2. Related Background Art
As shown in
FIG. 5
, a lithium battery
30
typically is connected with a protection circuit
40
for protecting the lithium battery
30
at the time of charging/discharging. Generally, the protection circuit
40
includes two MOS transistors MOS
1
and MOS
2
, drains of which are commonly connected, diodes
41
and
42
connected in parallel to the respective MOS transistors, and a protection resistor
45
, and is controlled by a control circuit
50
based on the potential across the lithium battery
30
.
When the lithium battery
30
is discharged, a load
60
connected in series with the protection circuit
40
is disconnected from a battery charger
70
. In this state, the control circuit
50
controls the protection circuit
40
so that a potential at an “H” level is applied to gates G
1
and G
2
of the MOS transistors MOS
1
and MOS
2
, and after the potential of the lithium battery
30
becomes below a predetermined level, the potential of the gate G
2
of the MOS transistor MOS
2
is lowered to an “L” level, as shown in FIG.
6
(
a
). When the lithium battery
30
is charged, the load
60
is connected in parallel with the battery charger
70
. In this state, the control circuit
50
controls the protection circuit
40
so that a potential at the “H” level is applied to the gates G
1
and G
2
of the MOS transistors MOS
1
and MOS
2
, and after the potential of the lithium battery
30
becomes below the predetermined level, the potential of the gate G
1
of the MOS transistor MOS
1
is lowered to the “L” level.
The protection circuit
40
having the above-described structure is sealed with mold resin on a common drain frame
85
to form a package
80
, as shown in FIG.
7
. Each of the MOS transistors MOS
1
and MOS
2
constituting the protection circuit
40
has a plurality of source terminals, as shown in FIG.
7
. Generally, a package sealed with mold resin is thick.
Recently, as mobile devices including lithium batteries therein have become more compact, thinner, and lighter, it has been strongly requested that the size of MOS transistors be reduced. Under the circumstances, CSPs (Chip Size Packages) have received attention as being the thinnest type of packages, which can replace rather-thick conventional packages sealed with mold resin.
As shown in
FIG. 3
, a CSP typically has such features that dicing is not performed between two MOS transistors MOS
1
and MOS
2
, and that solder balls
18
serving as electrodes are formed on the chip, which are connected to a gate G
1
and sources S
1
of the MOS transistor MOS
1
, and a gate G
2
and sources S
2
of the MOS transistor MOS
2
. CSPs having such a structure are expected to become the mainstream semiconductor devices for lithium battery protection circuits, since the height of such CSPs is considerably reduced as compared with conventional devices.
FIG. 4
shows a section view of a semiconductor device having the above-described CSP structure, taken along line A-A′ of FIG.
3
. This semiconductor device has a plurality of N-channel MOS transistors having a trench gate structure. In this semiconductor device, an N
−
epitaxial layer
4
having a high resistance is formed on an N
+
semiconductor substrate
2
serving as a drain; a P-type semiconductor layer
6
serving as a base is formed on the N
−
epitaxial layer
4
; and a plurality of N-channel MOS transistors are formed in the P-type semiconductor layer
6
. The structure of such MOS transistors will be described in detail with reference to
FIG. 2
, which is an enlarged view of the MOS transistors shown in FIG.
4
.
As shown in
FIG. 2
, N
+
semiconductor regions
8
, and P
+
semiconductor regions
10
for applying a predetermined potential to the P-type semiconductor layer
6
are formed near the surface of the P-type semiconductor layer
6
. A P
+
semiconductor region
10
is formed near the surface of the P-type semiconductor layer
6
between two N
+
semiconductor regions
8
so as to contact the N
+
semiconductor regions
8
. Further, the P-type semiconductor layer
6
includes trenches reaching the N
−
epitaxial layer
4
, in which gate electrodes
12
are formed via insulating films
14
, which are gate insulating films. An insulating film
16
is formed to cover each gate electrode
12
. The insulating film
16
does not completely cover the N
+
semiconductor regions
8
serving as sources, but exposes part of the surface of the sources
8
. A metal layer
17
is formed to cover the main surface of the substrate thus constituted. A predetermined potential is applied to the P-type semiconductor layer
6
and the N
+
semiconductor regions
8
via the metal layer
17
.
When a predetermined potential is applied to the gate electrodes
12
, electrons flow from the N
+
semiconductor regions
8
serving as the sources to the N
+
semiconductor substrate
2
serving as the drain, via the P-type semiconductor layer
6
serving as the base and the N
−
epitaxial layer
4
, as shown in FIG.
4
.
The MOS transistors MOS
1
and MOS
2
are isolated by an element isolation film
19
, as shown in FIG.
4
.
However, since the drain does not serve as an electrode in this CSP-structure semiconductor device as show in
FIGS. 3 and 4
, a current I
S1S2
flows through the interface between the epitaxial layer
4
and the silicon semiconductor substrate
2
, in the traverse direction from the transistor MOS
1
side to the transistor MOS
2
side. The reason for this is that although the resistivity of the silicon substrate
2
is about 3 m&OHgr;·cm, which is a few hundred times lower than that of the epitaxial layer
4
, the section area of the current path is small, and the traverse length of the chip is 1 mm or more, resulting in that the resistance value of the silicon substrate is increased. Due to such a feature, there is a problem in that ON resistance of this device is increased as compared with the case where a current flows in the vertical direction through each of the transistors MOS
1
and MOS
2
having the trench gate structure.
SUMMARY OF THE INVENTION
According to an embodiment of the present invention, a semiconductor device includes: a semiconductor substrate of a first conductive type; a first semiconductor layer of the first conductive type formed on a main surface of the semiconductor substrate, the impurity concentration of the first semiconductor layer being lower than that of the semiconductor substrate; a second and third semiconductor layers of a second conductive type formed on the first semiconductor layer, the second and third semiconductor layers being isolated from each other; a first MOS transistor of the first conductive type formed in the second semiconductor layer, the first semiconductor layer and the semiconductor substrate serving as drains of the first MOS transistor; a second MOS transistor of the first conductive type formed in the third semiconductor layer, the first semiconductor layer and the semiconductor substrate serving as drains of the second MOS transistor; and a conductive layer formed on a reverse surface of the semiconductor substrate.


REFERENCES:
patent: 5321289 (1994-06-01), Baba et al.
patent: 5925910 (1999-07-01), Menegoli
patent: 6057588 (2000-05-01), Yamazaki
patent: 6137135 (2000-10-01), Kubo et al.
patent: 6297101 (2001-10-01), Schaeffer
patent: 6509607 (2003-01-01), Jerred
patent: 19620625 (1997-10-01), None
patent: 9-260648 (1997-10-01), None
patent: 10-173175 (1998-06-01), None
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