MOS sample and hold circuit

Details MOS sample and hold circuit MOS sample and hold circuit

1998-04-29

2000-04-18

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

By amplitude

327 91, 327 95, 341122, G11C 2702, H03K 1700, H03K 500

Patent

active

060520000

ABSTRACT:
A MOS track-and-hold circuit incorporating cancellation of error due to switch feedthrough is described. To eliminate the channel charge feedthrough due to oxide capacitance, a switched capacitor source (22) is connected to be charged to a voltage V1 during the "hold" phase and between the input node (12) and the switch gate (17) to provide a voltage V1-Vin during the "track" phase. A dummy transistor (26) biased in an "off" condition has its drain connected to the holding capacitor (15) and its gate switched between ground and the output terminal (Vout which tracks Vin) to also cancel the feedthrough from the gate-drain overlap capacitance and any gate-drain parasitic capacitance.

REFERENCES:
patent: 5479121 (1995-12-01), Shen et al.
patent: 5570048 (1996-10-01), Rijns

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