MOS random memory array

Details MOS random memory array MOS random memory array

1977-04-19

1978-09-19

Konick, Bernard

Static information storage and retrieval

Systems using particular element

Capacitors

365 51, G11C 1124, G11C 702

Patent

active

041158717

ABSTRACT:
This disclosure relates to an MOS random access memory array which utilizes a very small memory cell having a single MOS device and a small size, high capacitance, semiconductor capacitor device connected together to form one bit or memory cell of an MOS dynamic, random access memory array. Preferably, either the source or drain region of the MOS device is connected to the semiconductor portion of the semiconductor capacitor device which is of the electrode-insulator-semiconductor type. The semiconductor capacitor has a very high capacitance due to the use of a very shallow arsenic (N type) implanted region within a boron (P type) implanted region so that the PN junction formed is located where the concentration of Boron impurities is high thereby increasing the capacitance of the semiconductor capacitor. For each memory cell of the memory array, one of the active regions of the MOS device, for example, the source region, is connected to a Bit/Sense line of the memory array. The semiconductor portion of the semiconductor capacitor is connected to the drain region of the MOS device and the electrode plate of the semiconductor capacitor device that is not connected to the drain region of the MOS device is connected to a word line which word line is the next adjacent word line of the MOS random access memory array. The gate of the MOS device is connected up to the word line for that MOS device.

REFERENCES:
patent: 3699537 (1972-10-01), Wahlstrom
patent: 3838404 (1974-09-01), Heeren
Sodini et al., "Enhanced Capacitor for One-Transistor Memory Cell," IEEE Transactions on Electron Devices, vol. Ed-23, No. 10, pp. 1187-1189, Oct. 1976.

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