MOS Random-access memory

Details MOS Random-access memory MOS Random-access memory

1979-08-27

1981-01-27

Hecker, Stuart N.

Static information storage and retrieval

Read/write circuit

Flip-flop used for sensing

365210, G11C 700, G11C 706

Patent

active

042479177

ABSTRACT:
An MOS dynamic random-access memory (RAM) realizable as a 64K RAM is disclosed. Single transistor cells employing capacitive storage are coupled to folded bit-line halves. These bit-line halves are connected to sense amplifiers employing cross-coupled transistors. Boosting means employing a variable capacitance are coupled to the bit-line halves to boost the potential on a line during reading. The capacitor associated with each of the memory cells is coupled to a potential which is greater than the power supply potential. This plate potential is substantially constant and independent of power supply variations and is internally generated. The dummy cells employed within the RAM are charged in a unique manner to a substantially constant potential which does not vary with power supply variations.

REFERENCES:
patent: 4038646 (1977-07-01), Mehta et al.
patent: 4081701 (1978-03-01), White et al.
patent: 4130897 (1978-12-01), Horne et al.
patent: 4158241 (1979-06-01), Takemae et al.
patent: 4198697 (1980-04-01), Kuo et al.

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