MOS Multi-layer neural network and its design method

Details MOS Multi-layer neural network and its design method MOS Multi-layer neural network and its design method

1991-08-15

1994-03-08

MacDonald, Allen R.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

395 24, 307201, G06F 1518

Patent

active

052934586

ABSTRACT:
Disclosed is a multi-layer neural network and circuit design method. The multi-layer neural network receiving an m-bit input and generating an n-bit output comprises a neuron having a cascaded pair of CMOS inverters and having an output node of the preceding CMOS inverter among the pair of CMOS inverters as its inverted output node and an output node of the succeeding CMOS inverter as its non-inverted output node, an input layer having m neurons to receive the m-bit input, an output layer having n neurons to generate the n-bit output, at least one hidden layer provided with n neurons to transfer the input received from the input layer to the directly upper hidden layer or the output layer, an input synapse group in a matrix having each predetermined weight value to connect each output of neurons on the input layer to each neuron of the output layer and at least one hidden layer, at least one transfer synapse group in a matrix having each predetermined weight value to connect each output of neurons of the hidden layer to each neuron of its directly upper hidden layer or of the output layer, and a bias synapse group for biasing each input node of neurons of the hidden layers and the output layer.

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McClelland et al., Explorations in Parallel Distributed Processing, MIT Press, 1988, 2-3, 121-145.
Walker et al., "A CMOS Neural Network for Pattern Association", IEEE Micro, Oct. 1989, 68-74.
Salam et al., "A Feed forward Neural Network for CMOS VLSI Implementation", Midwest Symposium on Circuits & Systems, Aug. 12-14, 1990, 489-492.
Graf et al., "VLSI Implementation of a Neural Network Model", Computer, Mar. 1988, 41-49.
Eberhardt et al., "Design of Parallel Hardware Neural Network Systems from Custom Analog VLSI `Building Block` Chips", IJCNN, Jun. 18-22, 1989, II-183 to II-190.

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