MOS Memory cell

Details MOS Memory cell MOS Memory cell

1980-01-31

1981-12-29

Hecker, Stuart N.

Static information storage and retrieval

Systems using particular element

Semiconductive

365149, G11C 1140, G11C 1124

Patent

active

043085946

ABSTRACT:
An integrated circuit memory cell (10) having a bit line (12), a word line (14) and a cell voltage supply (26) is provided. The integrated circuit memory cell (10) includes a first clock line (34) and a second clock line (36). A first transistor (20) is interconnected to the bit line (12) and the word line (14) for providing access to the memory cell (10). A second transistor (22) is interconnected to the cell voltage supply source (26) and to the first transistor (20) thereby defining a first node (S). The second transistor (22) provides a charging path from the cell voltage supply source (26) to the first node (S). A capacitor (30) is provided and interconnects the first clock line (34) and the second transistor (22). The interconnection between the capacitor (30) and the second transistor (22) defines a second node (K). The capacitor (30) provides a coupling path between the first clock line (34) and the second node (K) for conditionally supplying a voltage from the first clock line (34) to the second node (K) to render voltage at the second node (K) higher than the cell voltage supply source (26). A third transistor is provided for the memory cell (10) and is interconnected to the first node (S) and the second node (K) and the second clock line (36). The third transistor (24) provides a charging path between the second clock line (36) and the second node (K) for conditionally maintaining a voltage at the second node (K).

REFERENCES:
patent: 3618053 (1971-11-01), Hudson et al.
patent: 3744037 (1973-07-01), Spence
patent: 3876993 (1975-04-01), Cavanaugh
patent: 3878404 (1975-04-01), Walther et al.
patent: 3967252 (1976-06-01), Donnelly
patent: 4091460 (1978-05-01), Schuermeyer et al.
patent: 4125854 (1978-11-01), McKenny et al.
Caywood et al., "A Novel 4K Static RAM with Submilliwatt Standby Power," IEEE Trans. on Electron Dev., vol. ED-26, No. 6, 6/79, pp. 861-864.
Cilingiroglu", A Charge-Pumping-Loop Concept for Static MOS/RAM Cells", IEEE Jour. of Solid-State Cir., vol. SC-14, No. 3, 6/79, pp. 599-603.

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