Static information storage and retrieval – Read/write circuit – Including signal clamping
Patent
1997-10-23
1999-12-28
Nelms, David
Static information storage and retrieval
Read/write circuit
Including signal clamping
36518909, 326121, G11C 1604
Patent
active
060090219
ABSTRACT:
A MOS logic circuit is charged by adiabatic charging, and is composed of a clamp circuit having a pair of PMOS transistors, and two functional circuits, each having at least one NMOS transistor, a gate electrode of each of the NMOS transistors being an input node, one terminal of each functional circuit being connected to a common constant-voltage power source, and the other terminal of each functional circuit being connected to a drain electrode of the corresponding PMOS transistor, thus forming an output node. A substrate electrode of each of the NMOS transistors making up the two functional circuits is cross-connected to the output node of the other functional circuit. In this way, even in the HOLD operation, in which both input nodes fall to low level, the NMOS transistor which is to output low level becomes depletion mode, and the outputting operations are stabilized without increasing circuit size.
REFERENCES:
patent: 5877634 (1999-03-01), Hunley
Seitz et al, "Hot-Clock nMOS," Chapel Hill Conference on VLSI (1985) pp. 1-17.
Kramer et al., "2nd Order Adiabatic Computation with 2N-2P and 2N-2NP Logic Circuits, " ISLPD '95 Symposium Proceedings, pp. 191-196.
Assaderaghi et al., "A Dynamic Threshold Voltage MOSFET (DTMOS) for Ultra-Low Voltage Operation," IEEE (1994) , pp. 809-812.
Moon et al., "An Efficient Charge Recovery Logic Circuit," IEEE Journal of Solid-State Circuits, vol. 31, No. 4 (Apr. 1996) pp. 514-522.
Kioi et al, "forward body-bias MOS (FBMOS) dual rail logic using an adiabatic charging technique with sub-0.6V operation," Electronic Letters, vol. 33, No. 14 (Jul. 3, 1997) pp. 1200-1201.
Athas et al., "Low-Power Digital Systems Based on Adiabatic-Switching Principles," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 2, No. 4 (Dec. 1994) pp. 398-407.
Landauer, "Irreversibility and Heat Generation in the Computing Process," IBM Journal (Jul. 1961) pp. 183-191.
Kotaki et al., "Novel Bulk Dynamic Threshold Voltage MOSFET (B-DTMOS) with Advanced Isolation (SITOS) and Gate to Shallow-Well Contact (SSS-C) Processes for Ultra Low Power Dual Gate CMOS," IEEE (1996) pp. 459-462.
Lam David
Nelms David
Sharp Kabushiki Kaisha
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