MOS-Integrated circuit arrangement for suppressing quiescent cur

Details MOS-Integrated circuit arrangement for suppressing quiescent cur MOS-Integrated circuit arrangement for suppressing quiescent cur

1979-12-17

1982-08-31

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Noise suppression

365208, G11C 1140

Patent

active

043475884

ABSTRACT:
MOS integrated circuit arrangement for suppressing quiescent currents flowing in word line drivers of semiconductor memories, including respective controlled switches addressed by a storage activation signal, the controlled switches being connected between the output circuit of the word line drivers and reference potential.

REFERENCES:
patent: 4195239 (1980-03-01), Suzuki

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