MOS-gated transistor with reduced miller capacitance

Details MOS-gated transistor with reduced miller capacitance MOS-gated transistor with reduced miller capacitance

2007-09-04

2007-09-04

Prenty, Mark V. (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S340000

Reexamination Certificate

active

10962367

ABSTRACT:
In one embodiment of the present invention, a trench MOS-gated transistor includes a first region of a first conductivity type forming a pn junction with a well region of a second conductivity type. The well region has a flat bottom portion and a portion extending deeper than the flat bottom portion. A gate trench extends into the well region. Channel regions extend in the well region along outer sidewalls of the gate trench. The gate trench has a first bottom portion which terminates within the first region, and a second bottom portion which terminates within the deeper portion of the well region such that when the transistor is in an on state the deeper portion of the well region prevents a current from flowing through those channel region portions located directly above the deeper portion of the well region.

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