MOS gate array devices

Details MOS gate array devices MOS gate array devices

1988-05-02

1990-05-08

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Including specified plural element logic arrangement

36518911, 307465, 34082583, G11C 700, H03K 19177

Patent

active

049244400

ABSTRACT:
A MOS gate array has a PLA formed in a memory area which includes a plurality of first and second elementary unit circuits. The first elementary unit circuit includes two output lines, one input line, two PMOS transistors, and four NMOS transistors. The second elementary unit circuit includes two input lines, an output line, two PMOS transistors, and four NMOS transistors. Input lines are formed to extend substantially perpendicularly to the output lines. Thus, the PLA is constructed so as to have a high degree of integration.

REFERENCES:
patent: 3566153 (1971-02-01), Spencer, Jr.
patent: 4508977 (1985-04-01), Page et al.
patent: 4546273 (1985-10-01), Osman

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