Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2005-03-08
2005-03-08
Lee, Eddie (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S401000, C257S328000, C257S329000, C257S344000, C257S408000, C257S330000, C257S331000, C257S332000, C257S343000, C257S334000, C257S335000, C257S336000, C257S337000, C257S345000, C257S339000, C257S341000, C257S342000, C257S195000, C257S141000, C257S346000, C438S282000
Reexamination Certificate
active
06864533
ABSTRACT:
A semiconductor substrate includes a first principal plane and a second principal plane opposite this first principal plane. A first semiconductor region is formed on the first principal plane of the semiconductor substrate. Second and third semiconductor regions are formed separately from each other on the first semiconductor region. A gate electrode is formed, via a gate insulator, on the first semiconductor region between the second semiconductor region and the third semiconductor region. An electric conductor is formed up to the semiconductor substrate from the second semiconductor region and electrically connects the second semiconductor region with the semiconductor substrate. A first main electrode is formed on the second principal plane of the semiconductor substrate and is electrically connected to the semiconductor substrate. A second main electrode is formed on the first semiconductor region via insulators and is electrically connected to the third semiconductor region.
REFERENCES:
patent: 4794432 (1988-12-01), Yilmaz et al.
patent: 5155563 (1992-10-01), Davies et al.
patent: 5929488 (1999-07-01), Endou
patent: 5932897 (1999-08-01), Kawaguchi et al.
patent: 6002154 (1999-12-01), Fujita
patent: 6297533 (2001-10-01), Mkhitarian
patent: 6365915 (2002-04-01), Hirai et al.
patent: 6369425 (2002-04-01), Ferla et al.
patent: 4-18762 (1992-01-01), None
patent: 5-121739 (1993-05-01), None
patent: 6-97447 (1994-04-01), None
patent: 6-151846 (1994-05-01), None
patent: 8-227998 (1996-09-01), None
Isao Yoshida, et al., “Highly Efficient 1.5GHz Si Power MOSFET for Digital Cellular Front End”, Proceedings of 1992 International Symposium on Power Semiconductor Devices & ICs, Tokyo, 1992, pp. 156-157.
Shuming Xu, et al., “RF LDMOS with Extreme Low Parasitic Feedback Capacitance and High Hot-Carrier Immunity”, Tech. Dig. International Electron Devices Meeting, 1999, pp. 201-204.
Kawaguchi Yusuke
Nakagawa Akio
Nakamura Kazutoshi
Yasuhara Norio
Im Junghwa
Kabushiki Kaisha Toshiba
Lee Eddie
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
LandOfFree
MOS field effect transistor with reduced on-resistance does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with MOS field effect transistor with reduced on-resistance, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and MOS field effect transistor with reduced on-resistance will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3417680