MOS dynamic memory device

Details MOS dynamic memory device MOS dynamic memory device

1982-09-16

1986-06-03

Popek, Joseph A.

Static information storage and retrieval

Systems using particular element

Capacitors

365203, G11C 1124

Patent

active

045933820

ABSTRACT:
An MOS dynamic memory device is improved in operation by adding a cell plate voltage control circuit to terminals of the word lines and connected to respective cell plates. In operation, the cell plate is recharged after discharged during with a time which a word line remains driven.

REFERENCES:
patent: 3909631 (1975-09-01), Kitagawa
patent: 4061954 (1977-12-01), Proebsting et al.
patent: 4409672 (1983-10-01), Takemae
H. H. Chao et al., "A 34 .mu.m Dram Cell Fabricated with a 1 .mu.m Single Level Polycide FET Technology", Proceedings of the 1981 IEEE International Solid-State Circuits Conference, pp. 152, 153.
J. Y. Chan et al., "A 100 ns 5V Only 64K x 1 MOS Dynamic RAM", IEEE J. of Solid-State Circuits, vol. SC-15, pp. 839-846, Oct. 1980.
F. Yanagawa et al., "A 1-.mu.um Mo-Poly 64-kbit MOS RAM", IEEE Journal of Solid-State Circuits, vol. SC-15, pp. 667-671, Aug. 1980.

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