MOS driver circuit having clamp means to hold the output voltage

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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Details

307451, 307475, 307482, H03K 1716

Patent

active

050650491

ABSTRACT:
A MOS driver circuit comprises a pull-up NMOS transistor, a pull-down NMOS transistor, and a clamper circuit. The pull-up NMOS transistor has a source connected to an output terminal and a gate connected to a boosting node supplied with a boosted voltage when the output terminal is driven to a "high" state. The pull-down NMOS transistor has a drain connected to the output terminal and a source connected to the ground voltage, and is turned on when the output terminal is driven to a "low" state. The clamper circuit clamps the boosted voltage to a predetermined voltage by opening a current path from the boosting node to the output node when the boosted voltage supplied to the boosting node is greater than the predetermined voltage. In the circuit, the noise in the power and ground lines, which is generated due to the variation of the output voltage caused by the variation of the supply voltage, is prevented. Also, since the clamper circuit of the present invention discharges the charge of the boosting node to the output terminal, more charge can be discharged within short time during the transition from a low output state to a high state, thereby resulting in a more effective clamping operation.

REFERENCES:
patent: 4678944 (1987-07-01), Williams
patent: 4866308 (1989-09-01), Cecchi et al.
patent: 4972104 (1990-11-01), Estrada
patent: 4998029 (1991-03-01), Sundstrom

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