MOS devices with reduced fringing capacitance

Details MOS devices with reduced fringing capacitance MOS devices with reduced fringing capacitance

2002-09-27

2004-08-31

Ngô, Ngân V. (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S387000, C257S389000, C257S412000

Reexamination Certificate

active

06784491

ABSTRACT:

BACKGROUND
1. Field of the Invention
Embodiments of the invention relates to the field of semiconductor, and more specifically, to semiconductor fabrication.
2. Description of Related Art
The total capacitance of Metal Oxide Semiconductor (MOS) devices includes a number of different types of capacitance. The two types of capacitance that have significant effect on the switching time of MOS devices are the gate capacitance and the fringing capacitance. As gate lengths reduce, these capacitances also reduce. However, when the gate length reaches 0.05 micron and beyond, the capacitances do not reduce equally. Since the polysilicon lines become thinner as the gate length decreases, the gate capacitance decreases but the fringing capacitance does not decrease as rapidly. Typically, at the 30 nm gate length dimensions, the fringing capacitance can add up to one-third of the total capacitance.
One way to reduce the fringing capacitance is to reduce the height of the polysilicon layer. However, reducing the polysilicon height only slightly reduces the fringing capacitance because it merely removes the longest field lines having the smallest capacitance. The majority of the shorter field lines with large capacitance still remains. Reducing the polysilicon height also adds complexity to the fabrication process.


REFERENCES:
patent: 5834816 (1998-11-01), Jang
patent: 6025235 (2000-02-01), Krivokapic
patent: 6169315 (2001-01-01), Son
patent: 6307226 (2001-10-01), Dennison
patent: 6316811 (2001-11-01), Pey
Prof. A. Mason, Overview of Semiconductor Fabrication Technology, article, 5 pages.

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