MOS device with self-compensating V.sub.aT -implants

Details MOS device with self-compensating V.sub.aT -implants MOS device with self-compensating V.sub.aT -implants

1997-10-14

2000-08-01

Chaudhuri, Olik

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having schottky gate

438217, 438290, 438525, 438230, 257402, H01L 2976, H01L 218238, H01L 21336, H01L 218249

Patent

active

06096586&

ABSTRACT:
There is provided a MOS device with self-compensating threshold implant regions and a method of manufacturing the same which includes a semiconductor substrate, a partial first threshold implant forming a higher concentration layer, a gate oxide formed on the surface of the higher concentration layer, and a gate formed on a surface of the gate oxide. The MOS device further includes a second threshold implant for forming self-compensating implant regions in the substrate which is subsequently heated to define pockets. A third implant is performed to create lightly-doped source/drain regions. A sidewall spacer is formed on each side of the gate. A fourth implant is performed to create highly-doped source/drain regions between the lightly-doped source/drain regions and the pockets.

REFERENCES:
patent: 5091763 (1992-02-01), Sanchez
patent: 5843825 (1998-12-01), Hwang
patent: 5844276 (1998-12-01), Fulford, Jr. et al.
patent: 5847428 (1998-12-01), Fulford, Jr. et al.
"Source-to-Drain Nonuniformly Doped Channel (NUDC) MOSFET Sturctures for High Current Drivability and Threshold Voltage Controllability", Okumura et al., IEEE Transaction on Electron Devices, vol. 39, No. 11, Nov. 1992, pp. 2541-2552.
S. Wolf and R.N. Tauber, Silicon Processing for the VLSI Era, vol. 1, Lattice Press, pp. 303-308 and 242-256, 1986.

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