MOS device having a passivated semiconductor-dielectric...

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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C438S910000

Reexamination Certificate

active

06603181

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to MOS devices and their fabrication. More particularly, this invention relates to MOS devices that employ metal gate electrodes over ultra-thin gate dielectrics, and to a process for passivating the semiconductor-dielectric interface of such devices by diffusing atomic hydrogen through the metal gate electrode.
2. Description of the Prior Art
With the continued scaling of MOSFET (metal-oxide-semiconductor field effect transistors) gate lengths to the tens of nanometers regime, metal gate electrodes have been studied extensively as a substitute for conventional polysilicon gates to eliminate polysilicon gate depletion and to reduce gate resistance. Preferred materials for metal gate electrodes have been those with a midgap workfunction, i.e., a Fermi level midway between the valence and conduction bands of the semiconductor material (e.g., silicon), in order to implement CMOS with slightly doped and undoped channels. For devices with gate lengths well below 0.1 micrometer, a gate material with a midgap workfunction is desirable to permit the use of lightly-doped channels in fully depleted, ultra-thin CMOS-SOI (metal-oxide-semiconductor, silicon-on-insulator) devices. This approach minimizes threshold voltage variations that may occur from device to device as a result of fluctuations in local dopant concentration and film thickness, and increases the carrier mobility from reduced impurity scattering and normal electric fields. Tungsten is one of the most promising candidates for metal gate CMOS technology because of its low resistivity and near ideal midgap workfunction. In addition, the refractivity of tungsten permits process integration in the very early stages of the standard CMOS technology. For deposition on ultra-thin dielectrics, chemical vapor deposition (CVD) has been successfully employed as the method for producing thin, low-resistivity tungsten gate electrodes. Although there have been studies on the performance of tungsten gate MOSFET's, the CVD tungsten gate MOS interface has not been examined in great detail.
For all high performance MOS devices, the passivation of the semiconductor-dielectric interface is important. In the art it is known that, for a MOS capacitor comprising a silicon substrate, silicon dioxide dielectric film and an aluminum electrode, heating the MOS structure to a temperature of about 350° C. to about 500° C. in either a nitrogen or hydrogen environment is able to reduce the Si/SiO
2
interface state (trap) density (D
ito
) to very low levels, e.g., less than 5×10
10
/cm
2
-eV. The effectiveness of aluminum in this process has been attributed to atomic hydrogen produced by the reaction of aluminum with water vapor adsorbed at the Al-SiO
2
interface. In theory, atomic hydrogen passivates the Si/SiO
2
interface by tying up dangling bonds. In contrast, interface states in polysilicon gate MOS devices can be passivated with forming gas anneal (FGA) treatments using 5 to 10% hydrogen and 90 to 95% nitrogen at temperatures of about 400° C. to about 550° C. However, it has been observed that standard FGA treatments provide very little passivation of a Si/SiO
2
interface (e.g., an interface state density below 5×10
11
/cm
2
-eV) when applied to MOS capacitors with 100 nm thick CVD tungsten gate electrodes. One possible explanation is where a high temperature (e.g., about 500° C. or more) hydrogen-free CVD process has been used, which may effectively eliminate any internal source of hydrogen. Another possibility might lie in the low solubility and diffusivity of hydrogen gas in tungsten, such that a tungsten electrode prevents molecular hydrogen within the surrounding atmosphere from reaching the Si/SiO
2
interface during annealing. In any event, the inability to passivate the semiconductor-dielectric interface through a tungsten layer is a potential barrier to the practical use of MOS devices (including capacitors and FET's) with thick tungsten gate electrodes.
From the above, it can be seen that it would be desirable if a process were available to reduce the semiconductor-dielectric (Si/SiO
2
) interface state density of a MOS device with a thick tungsten gate electrode, particularly if such a process were capable of reducing the interface state density to very low levels (for example, below 5×10
10
/cm
2
-eV).
BRIEF SUMMARY OF THE INVENTION
The present invention provides a process for passivating the semiconductor-dielectric interface of a MOS structure to reduce the interface state density to a very low level. More particularly, the invention is directed to MOS structures that employ a metal layer, and particularly a tungsten layer, that in the past has prevented passivation of an underlying semiconductor-dielectric interface to an extent sufficient to yield an interface state density of less than 5×10
10
/cm
2
-eV.
The invention generally entails fabricating a MOS device by forming a layer of a suitable dielectric material (such as silicon dioxide) on a silicon-containing semiconductor substrate, such that a semiconductor-dielectric interface is formed between the substrate and the dielectric layer. A metal layer that is pervious to atomic hydrogen is then formed on the dielectric layer to yield a MOS structure. The MOS structure is then exposed to atomic hydrogen in a manner that diffuses the atomic hydrogen through the metal layer and into the interface. The invention encompasses several approaches for introducing atomic hydrogen into the semiconductor-dielectric interface. According to one technique, an aluminum layer is formed on the metal layer in the presence of hydrogen to form a metal stack in which atomic hydrogen is stored between the metal and aluminum layers. The MOS structure is then annealed at a temperature sufficient to cause the atomic hydrogen to diffuse through the metal layer and into the interface. In a second technique, atomic hydrogen is diffused through the metal layer and into the interface by subjecting the metal layer to hydrogen plasma. Another technique is to implant atomic hydrogen into the metal layer, and then anneal the MOS structure at a temperature sufficient to cause the atomic hydrogen to diffuse through the metal layer and into the interface.
According to the invention, sufficient atomic hydrogen is diffused into the semiconductor-dielectric interface to passivate the interface, preferably yielding an interface state density of less than 5×10
10
/cm
2
-eV. The process of this invention is particularly beneficial to MOSFET devices that employ metal gates, and particularly tungsten gates, over an ultra-thin gate dielectric, e.g., silicon dioxide at thicknesses of 5 nm or less. Of particular significance to the invention are tungsten layers that are deposited to thicknesses of greater than 20 nm. The present invention determined that such tungsten gates are substantially impervious to molecular hydrogen, thereby preventing the passivation of an underlying semiconductor-dielectric interface by methods employed by the prior art, yet pervious to atomic hydrogen so as to allow passivation in accordance with the techniques of this invention. Consequently, the present invention makes possible MOSFET's with short gate lengths (e.g., on the order of 0.01 micrometer or less) and which make use of tungsten as the gate electrode material, such that the electrode has a midgap workfunction to permit the use of lightly-doped channels in fully depleted, ultra-thin CMOS-SOI devices.
Other objects and advantages of this invention will be better appreciated from the following detailed description.


REFERENCES:
patent: 3849204 (1974-11-01), Fowler
patent: 3852120 (1974-12-01), Johnson et al.
patent: 4447272 (1984-05-01), Saks
patent: 4505028 (1985-03-01), Kobayashi et al.
patent: 4840917 (1989-06-01), Sheu
patent: 4952523 (1990-08-01), Fujii
patent: 5289030 (1994-02-01), Yamazaki et al.
patent: 5498557 (1996-03-01), Negishi et al.
patent: 5530293 (1996-06-01), Cohen et al.
patent: 578931

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