MOS device and process for manufacturing MOS devices using...

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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C257S316000, C257S321000, C257S365000, C257S377000, C438S257000, C438S258000, C438S266000

Reexamination Certificate

active

07023047

ABSTRACT:
An MOS device has a stack and a passivation layer covering the stack. The stack is formed by a first polysilicon region and by a second polysilicon region arranged on top of one another and separated by an intermediate dielectric region. An electrical connection region, formed by a column structure substantially free of steps, extends through the passivation layer, the second polysilicon region and the intermediate dielectric region, and terminates in contact with the first polysilicon region so as to electrically contacting the first polysilicon region and the second polysilicon region. Fabrication of the electrical connection region requires just one mask.

REFERENCES:
patent: 4719184 (1988-01-01), Cantarelli et al.
patent: 5326999 (1994-07-01), Kim et al.
patent: 5851880 (1998-12-01), Ikegami
patent: 6387745 (2002-05-01), Onoda et al.
patent: 6548857 (2003-04-01), Dalla Libera et al.
patent: 6680514 (2004-01-01), Geffken et al.
patent: 2002/0127802 (2002-09-01), Goda et al.
patent: 0 996 162 (2000-04-01), None
U.S. Appl. No. 10/745,297, filed Dec. 23, 2003, Caimi et al.

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