MOS decoder circuit implemented using a neural network architect

Details MOS decoder circuit implemented using a neural network architect MOS decoder circuit implemented using a neural network architect

1990-08-28

1992-12-01

Fleming, Michael R.

Boots, shoes, and leggings

395 24, 364602, 364807, G06F 1518

Patent

active

051685515

ABSTRACT:
A decoder circuit based on the concept of a neural network architecture has a unique configuration using a connection structure having CMOS inverters, and PMOS and NMOS bias and synapse transistors. The decoder circuit consists of M parallel inverter input circuit corresponding to an M-bit digital signal and forming an input neuron group, a 2.sup.M parallel inverter output circuit corresponding to 2.sup.M decoded outputs and forming an output neuron group, and a synapse group connected between the input neuron group and the output neuron group responsive to a bias group and the M-bit digital original for providing a decoded output signal to one of the 2.sup.M outputs of the output neuron group when a match is detected. Hence, only one of the 2.sup.M outputs will be active at any one time.

REFERENCES:
patent: 4876534 (1989-10-01), Mead et al.
patent: 4904881 (1990-02-01), Castro
patent: 4956564 (1990-09-01), Holler et al.
patent: 4962342 (1990-10-01), Mead et al.
patent: 4978873 (1990-12-01), Shoemaker
patent: 4988891 (1991-01-01), Mashiko
McClelland et al., Explorations in Parallel Distributed Processing: A Handbook of Models, Programs, and Exercises, The MIT Press, 1988, pp. 83-99.
Walker et al., "A CMOS Neural Network for Pattern Association", IEEE Micro, Oct. 1989, pp. 68-74.
Salam et al., "A Feedforward Neural Network for CMOS VSLI Implementation", Midwest Sympos. on Cir. Syst., 1990, pp. 489-492.
Graf et al., "VLSI Implementation of a Neural Network Model", Computer, Mar. 1988, pp. 41-49.
Tanenbaum, A. S., Structured Computer Organization, Prentice-Hall, Inc., 1984, pp. 121-122.

Affiliated with

Also associated with

Rating

MOS decoder circuit implemented using a neural network architect does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with MOS decoder circuit implemented using a neural network architect, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and MOS decoder circuit implemented using a neural network architect will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-508130