MOS/CMOS memory cell

Details MOS/CMOS memory cell MOS/CMOS memory cell

1985-02-07

1987-07-07

Larkins, William D.

Static information storage and retrieval

Systems using particular element

Flip-flop

357 239, 357 41, 357 59, 357 84, G11C 1140, H01L 2704, H01L 2978

Patent

active

046791710

ABSTRACT:
A memory array of four-IGFET-transistor cells arranged in rows and columns. The array uses two patterned metal layers and two patterned poly-silicon layers. For each column there is a pair of metal differential bit lines, formed on a first patterned metal layer. For each row there is a pair of split equipotential poly-silicon word lines and a parallel metal word line with connections to the split poly word lines at defined intervals. The parallel metal word line is on a second patterned metal layer distinct from the metal layer used for the bit lines. A grounded poly-silicon plate overlies the capacitive memory nodes of said array. The grounded poly-silicon plate is on a second patterned poly-silicon layer distinct from the poly-silicon layer used for the split word lines. The poly-silicon plate is connected to the circuit ground at defined intervals. Also, the poly-silicon plate provides alpha particle protection to the array and helps decouple the bit lines from the capacitive nodes of the array.

REFERENCES:
patent: 4234889 (1980-11-01), Raymond, Jr. et al.
patent: 4481524 (1984-11-01), Tsujide

Affiliated with

Also associated with

Rating

MOS/CMOS memory cell does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with MOS/CMOS memory cell, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and MOS/CMOS memory cell will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1666653