MOS channel device with counterdoping of ion implant for reduced

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

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257345, 257376, 257402, 257403, 257590, 257657, 257917, H01L 2976

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active

055481485

ABSTRACT:
An N-channel and P-channel MOSFET include counterdoping of a threshold voltage (V.sub.T) ion implant for reducing substrate sensitivity and source/drain junction capacitance. An arsenic (As) compensated boron (B) implant is provided in the N-channel MOSFET. A boron (B) compensated arsenic (As) implant is provided in the P-channel MOSFET.

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patent: 5141882 (1992-08-01), Komori et al.
Carlson et al., "Reduced Substrate Sensitivity in Field-Effect Transistors," IBM Technical Disc. Bulletin, vol. 16, No. 3, pp. 1022-1023, Aug. 1973.
Dally et al., "Sub-Micron Channel Length CMOS Technology," IBM Technical Disclosure Bulletin, vol. 33, No. 4, pp. 227-232, Sep. 1990.
Chao et al., "Fabrication Procedure for MOSFET Logic Integrated Circuit with Very Thin Gate Oxide." IBM Technical Disclosure Bulletin, vol. 22, No. 11, pp. 5152-5123, Apr. 1980.

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