Monostabilized dynamic programmable logic array in CMOS technolo

Details Monostabilized dynamic programmable logic array in CMOS technolo Monostabilized dynamic programmable logic array in CMOS technolo

1992-10-30

1993-12-28

Westin, Edward P.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307469, 307451, H03K 19173, H03K 19094

Patent

active

052742822

ABSTRACT:
The circuit includes an input register (RI); an output register (RU); an AND plane; and an OR plane. The AND plane has vertical lines (Y), which are controlled by the input register, and horizontal lines (L), which include transistors (TA) arranged in series and controlled by respective vertical lines. The horizontal lines are connected to ground by normally-off transistors (TV) and to the power supply by normally-on transistors (TP). These transistors (TV, TP) are controlled by a first clock signal (CK1.about.). The OR plane has horizontal lines (S) and vertical lines (U). The vertical lines (U) of the OR plane contain normally-off transistors (TO) which are controlled by respective horizontal lines of the OR plane. Horizontal lines of the AND plane and horizontal lines of the OR plane are connected by respective pairs of normally-on transistors (TB) and normally-off transistors (TC) arranged in series between the power supply and ground. In each pair, the normally-on transistor is controlled by a horizontal line of the AND plane, and the normally-off transistor is controlled by a second clock signal (CK2). A horizontal line of the OR plane is connected to the node between the pair. The vertical lines of the OR plane are connected to the power supply by respective transistors (TR), which are controlled by a third clock signal (CK2.about.), and to the output register by pass transistors (P), which are controlled by a fourth clock signal (CK3.about.).

REFERENCES:
patent: 4611133 (1986-09-01), Peterson et al.
patent: 4661728 (1987-04-01), Kashimura
patent: 4769562 (1988-09-01), Ghisio
patent: 4952824 (1990-08-01), Kamuro
patent: 5021690 (1991-06-01), Linz
patent: 5101122 (1992-03-01), Shinonara
Kraft et al., "OR Array Reduction Techniques," vol. 23, No. 8 IBM Tech. Disclo. Bull. (Jan. 1981) pp. 3533-3534.

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