Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2006-03-21
2006-03-21
Munson, Gene M. (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S324000, C257S411000, C257S900000
Reexamination Certificate
active
07015542
ABSTRACT:
A semiconductor device having a memory region in which a memory cell array is formed of non-volatile memory devices arranged in a matrix of plurality of rows and columns. Each of the non-volatile memory devices has: a word gate formed above a semiconductor layer with a gate insulating layer interposed; an impurity layer formed in the semiconductor layer to form a source region or a drain region; and sidewall-shaped control gates formed along both side surface of the word gate. Each of the control gates consists of a first control gate and a second control gate adjacent to each other. The first control gate and the second control gate are respectively formed on insulating layers having different thickness.
REFERENCES:
patent: 4997781 (1991-03-01), Tigelaar
patent: 5408115 (1995-04-01), Chang
patent: 5422504 (1995-06-01), Chang et al.
patent: 5494838 (1996-02-01), Chang et al.
patent: 5838041 (1998-11-01), Sakagami et al.
patent: 5969383 (1999-10-01), Chang et al.
patent: 6177318 (2001-01-01), Ogura et al.
patent: 6248633 (2001-06-01), Ogura et al.
patent: 6255166 (2001-07-01), Ogura et al.
patent: 6335554 (2002-01-01), Yoshikawa
patent: 6413821 (2002-07-01), Ebina et al.
patent: 6518124 (2003-02-01), Ebina et al.
patent: 6531350 (2003-03-01), Satoh et al.
patent: 6627461 (2003-09-01), Chapman et al.
patent: 6656794 (2003-12-01), Shibata
patent: 6664155 (2003-12-01), Kasuya
patent: 6706579 (2004-03-01), Kasuya
patent: 6707079 (2004-03-01), Satoh et al.
patent: 6709922 (2004-03-01), Ebina et al.
patent: 6750520 (2004-06-01), Kurihara et al.
patent: 6787417 (2004-09-01), Inoue
patent: 6809374 (2004-10-01), Takamura
patent: 6809385 (2004-10-01), Ebina et al.
patent: 6812520 (2004-11-01), Ebina et al.
patent: 6815291 (2004-11-01), Kasuya
patent: 6818507 (2004-11-01), Ueda
patent: 6849553 (2005-02-01), Inoue
patent: 2003/0057505 (2003-03-01), Ebina et al.
patent: 2003/0060011 (2003-03-01), Ebina et al.
patent: 2003/0157767 (2003-08-01), Kasuya
patent: 2004/0072402 (2004-04-01), Inoue
patent: 2004/0072403 (2004-04-01), Inoue
patent: 2004/0097035 (2004-05-01), Yamamukai
patent: 2004/0129972 (2004-07-01), Kasuya
patent: 2004/0135196 (2004-07-01), Kasuya
patent: A 6-338620 (1994-12-01), None
patent: A 7-161851 (1995-06-01), None
patent: B1 2978477 (1999-09-01), None
Hayashi et al. “Twin MONOS Cell with Dual Control Gates”, 2000 Symposium on VLSI Technology Digest of Technical Papers.
Chang et al. “A New SONOS Memory Using Source-Side Injection for Programming”, IEEE Electron Device Letters, vol. 19, No. 7, Jul. 1998, pp. 253-255.
Chen et al. A Novel Flash Memory Device with S Plit Gate Source Side Injection and ONO Charge Storage Stack (SPIN), 1997 Symposium on VLSI Technology Digest of Technical Papers, pp 63-64.
Munson Gene M.
Oliff & Berridge PLLC
Seiko Epson Corporation
LandOfFree
MONOS memory device does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with MONOS memory device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and MONOS memory device will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3532606