Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Patent
1998-10-05
2000-12-26
Dang, Trung
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
257317, 257321, H01L 27148
Patent
active
061664103
ABSTRACT:
The present invention provides a structure and method of manufacturing split gate MONOS multi-level logic memory device. The memory device has a poly stacked gate transistor 20A in series with a MONOS transistor 24A. The device has a novel operation to achieve multi-level memory storage (e.g., 4 voltage states). The method begins by forming a tunnel oxide layer 30 on the surface of a semiconductor substrate 10. The substrate having a stacked gate channel area 20 and a MONOS channel area 24 in the active regions. A poly floating gate electrode 32 is formed over the stacked gate channel region 20. A ONO layer having a memory nitride layer is formed over the floating gate 32 and the tunnel oxide layer over the MONOS channel region 24. A control gate electrode 44 is formed over the ONO layer 41 spanning across the poly floating gate electrode 32 and the MONOS channel region 24. Source/drain regions 50 51 are formed in the substrate. A poly flash transistor 20A and a MONOS flash transistor 24A combine to form the 4 level logic memory cell of the invention.
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Nozaki et al, "A 1-Mb EEPROM With MONOS Memory Cell For Semiconductor Disk Application," IEEE Journal of Solid State Circuits, vol. 26, No. 4, Apr. 1991, p. 498.
Hsu Ching-Hsiang
Liang Mong-Song
Lin Ruei-Ling
Ackerman Stephen B.
Dang Trung
Kebede Brook
Saile George O.
Stoffel William J.
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